Biasing scheme for FIFO memories

DETAILED DESCRIPTION Accordingly, it is a general object of the present invention to provide an improved biasing circuit for intermittent memories which is relatively simple and economical to manufacture and assemble, but yet overcomes the disadvantage of the prior art biasing circuits.
It is an object of the present invention to provide a biasing circuit for intermittent memories so as to compensate for leakage current without consuming any power.
It is another object of the present invention to provide a biasing circuit for use with memory cells in intermittent memories which includes an N-channel MOS biasing transistor and a cross-coupled half-latch circuit to continuously bias the bit-lines during a read operation so as to compensate for leakage.
In accordance with these aims and objectives, the present invention is concerned with the provision of a biasing circuit for use with memory cells in intermittent memories in which data can be written into and sensed in the memory cell which includes a memory cell, an N-channel MOS biasing transistor, and a cross-coupled half-latch circuit.
The memory cell is coupled with a word line and between first and second bit-lines at corresponding first and second sense nodes.
The N-channel transistor has its gate and drain connected to a supply potential.
The cross-coupled half-latch circuit is formed of a first P-channel MOS transistor and a second P-channel MOS transistor.
The first P-channel transistor has its source connected to the sources of the second P-channel transistor and the N-channel transistor.
The first P-channel transistor has its gate connected to the drain of the second P-channel transistor and to the second bit-line.
The second P-channel transistor has its gate connected to the drain of the first P-channel transistor and to the first bit-line.