Binary MOS ripple-carry parallel adder/subtracter and adder/subtracter stage suitable therefor

DETAILED DESCRIPTION What is claimed: 1.
A parallel adder/subtracter employing enhancement-mode insulated-gate field-effect transistors for combining a plurality of numbers each represented by a plurality of parallel bits, comprising: a plurality of binary ripple-carry parallel adders/subtracters, each operating on a pair of digital words coupled thereto, each of said adders/subtracters forming partial sum outputs, each of said plurality of adders/subtracters including a plurality of adder/subtracter stages the partial sum outputs from each stage coupled to the succeeding stage, each said stage being responsive to a different bit of an associated one of said pairs of digital words; each of said stages comprises a full adder, said full adder having a first input receiving a bit of a first one of said pair of digital words and having a second input; and switching section means having a first input receiving a bit of the second one of said pair of digital words and having an output coupled to said full adder second input, said switching section means being selectively operable to invert or not invert said bit of the second one of said pair of digital words in response to switching signals; an input delay means for coupling said two numbers to said first one of said adder/subtracters such that each bit of a first of said two numbers and each bit of a second of said numbers is delayed by one predetermined time period greater than the preceding lower order bit of said first number and the preceding lower order bit of said second number, respectively; a plurality of sum output terminals; and an output delay means for coupling the outputs of a last one of said plurality of adder/subtracters to said plurality of sum output terminals such that each output bit of said last adder/subtracter is delayed by one predetermined time period greater than the succeeding higher order output bit.
2.
A parallel adder/subtracter in accordance with claim 1, wherein said predetermined time period is the time required for generation of a carry in one of said full adders