Binary data encoding and decoding process

DETAILED DESCRIPTION Briefly stated, the present invention is a binary data encoding process comprising the steps of: applying a binary data sequence; separating the applied binary data sequence at every two bits; converting the binary data sequence separated at every two bits into a 3-bit code sequence according to a prescribed conversion algorism.
If the binary data sequence separated at every two bits are represented as {D.
sub.
2n, D.
sub.
2n+1 } (0<n<.
infin.
) and the converted 3-bit code sequence are represented as {M.
sub.
3n, M.
sub.
3n+1, M.
sub.
3n+2 } (0<n<.
infin.
), and a definition is given as Y.
sub.
n =D.
sub.
2n+1 .
times.
D.
sub.
2(n+1) Z.
sub.
n =M.
sub.
3n +M.
sub.
3n+1 +M.
sub.
3n+2 the prescribed conversion algorism is represented by the following equations: M.
sub.
3n =D.
sub.
2n .
times.
(Y.
sub.
n-1 +Z.
sub.
n-1) M.
sub.
3n+1 =M.
sub.
3n .
times.
M.
sub.
3n+2 .
times.
(Y.
sub.
n-1 +Z.
sub.
n-1) M.
sub.
3n+2 =D.
sub.
2n+1 .
times.
(Y.
sub.
n-1 +Z.
sub.
n-1).
times.
(Y.
sub.
n +Y.
sub.
n .
times.
D.
sub.
2(n+1)+1) According to another aspect of this invention, a binary data decoding process for decoding a 3-bit code sequence encoded by said binary data encoding process comprises the steps of: separating the 3-bit code sequence at every three bit; decoding the 3 bit code sequence separated at every three bits into a binary data sequence according to a prescribed conversion algorism.
The prescribed algorism is represented by the following equations: D.
sub.
2n =M.
sub.
3n +Z.
sub.
n D.
sub.
2n+1 =Z.
sub.
n+1 +M.
sub.
3n+2 .
times.
Z.
sub.
n+1 +Z.
sub.
n .
times.
M.
sub.
3(n-1)+2 According to yet another aspect of the present invention, a binary data decoding process further comprises the step of generating a flag signal for representing that the decoded binary data is erroneous.
Therefore, a primary object of this invention is to provide a binary data encoding and decoding process which mitigates the drawbacks of the conventional (1, 7) RLLC system while maintaining the same Figure of Merit as that of said conventional (1, 7) RLLC system.
Another object of this invention is to limit the propagation of error bits on the occasion of an error