Bipolar memory cell

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG.
1, a memory cell in accordance with the present invention is shown which is suitable to be fabricated in monolithic integrated circuit form.
Emitter 11 of multi-emitter NPN transistor 12 is connected to stand-by current drain line 13.
Current source 14 is connected to stand-by current drain line 13 in a manner known to those skilled in the art.
Emitter 15 of transistor 12 is connected to bit line 16.
Emitter 17 of multi-emitter NPN transistor 18 is connected to stand-by current drain line 13 and emitter 19 of transistor 18 is connected to bit line 21.
The base of transistor 12 is connected to the collector of transistor 18 and the collector of PNP transistor 22.
The base of transistor 18 is connected to the collector of transistor 12 and the collector of PNP transistor 23.
NPN transistor 24 has its emitter connected to the collector of transistor 12 and the base of transistor 22.
NPN transistor 25 has its emitter connected to the collector of transistor 18 and the base of transistor 23.
Select line 26 is connected to the emitters of transistors 22 and 23 and to the collectors and bases of transistors 24 and 25.
When a logical low signal appears on bit line 16 and a logical high signal appears on bit line 21, transistor 12 is on and transistor 18 is off due to the respective voltages at their bases.
When the low and high signals of the bitlines 16 and 21 are removed, the latched state is maintained by the low current from emitter 11 of transistor 12.
When the signals on bit lines 16 and 21 are reversed, i.
e.
high and low respectively, transistor 12 is off and transistor 18 is on.
When the high and low signals are removed, the latched state is maintained by the low current from emitter 17 of transistor 18.
The advantages of the present invention may be better understood by now referring to FIG.
2 which illustrates how a half cell, or transistors 12, 22, and 24 may be monolithically integrated in order to provide faster write pulse width and write recovery times