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Branch prediction and resolution apparatus for a superscalar computer processor
| Details |
Inventors: Grochowski, Edward T.; Alpert, Donald B.; Mills, Jack D.; Weiser, Uri C.;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Treat; William M.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction. |
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DETAILED DESCRIPTION The present invention provides an apparatus and method for improving the performance of superscalar pipelined computers using branch prediction.
The described embodiment has two instruction processing paths, or "pipelines" and a branch instruction can be executed in either pipeline, subject to restrictions described further herein.
In the first pipeline, the takenness and target of a branch instruction is known in the execution stage.
In the second pipeline, the target of a branch instruction is known in the execution stage, but the takenness may not be known until after the execution stage.
In order to allow a branch instruction in one of the pipelines to be paired with an instruction in the other pipeline, a way of handling branches that are resolved in one of the separate stages is provided.
Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
"Branch prediction" is a means of speculatively filling a pipeline with instructions at the target of a branch before it is known whether the branch will be taken and before the target address is known.
The present invention may be embodied in an apparatus for predicting a branch location in a sequence of instructions in a superscalar microprocessor that has a first and second pipeline, either of which can execute a branch instruction.
A branch target buffer is provided to store branch predictions that are supplied to an address selector for the prefetch unit, in response to an address in the pipeline indicative of a branch instruction.
The branch target buffer includes a plurality of entries having a tag field for storing a tag indicative of the address of a branch instruction, an address field for storing a target address predicted for the branch instruction, and a history field for storing a history of the branch takenness.
The history field may be dual ported for both reading and writing in a single clock cycle.
Also, the tag field may store the address of an instruction preceding a branch instruction, rather than the address of the branch instruction itself
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I/O Systems 
