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Broadband signal switching matrix network
| Details |
Inventors: Trumpp, Gerhard; Wolkenhauer, Jan;
Assignee: Siemens Aktiengesellschaft (Munich, DE)
Primary Examiner: O'Shea; Sandra L.
Assistant Examiner: Magistre; Dervis
Attorney, Agent or Firm: Hill, Steadman & Simpson
In a broadband signal switching matrix network having a cross-point matrix in FET technology whose switching elements, controlled by a holding memory cell, are each formed with a series circuit of a switching transistor and of an input transistor. Matrix output lines thereof are respectively connected to one terminal of the operating voltage source via a pre-charging transistor that is controlled by a pre-charging clock, that side of the series circuit connected opposite from the matrix output line being permanently connected to the other terminal of the operating voltage source (directly or via a transistor controlled by the output signal and individually associated to the matrix output line) in order to avoid sample clock lines that lead to the switching elements. |
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DETAILED DESCRIPTION An object of the present invention is to provide a broadband signal switching matrix network having limited dissipated power given adequate protection against disruption in which such disadvantages are avoided.
The present invention is directed to a broadband signal switching matrix network having a cross-point matrix in FET technology whose inputs can each be provided with an input driver circuit, whose outputs can each be provided with an output amplifier circuit, and each of whose switching elements controlled by a holding memory cell is respectively formed with a series circuit of a switching transistor whose control electrode is charged with a through-connect signal or inhibit signal and an input transistor that has its control electrode connected to the appertaining matrix input line.
The series circuit has the main electrode of one transistor, that is connected opposite from the series circuit, connected to the appertaining matrix output line, the matrix output line being connected to a pre-charging potential source via a pre-charging circuit that has an unlocking input connected to the clock signal line of a pre-charging clock signal that defines the pre-charging phase of a bit through-connect time span that is subdivided into such a pre-charging phase and into the remaining bit through-connection time span.
As a result the matrix output line is charged to a pre-charging potential in every pre-charging phase.
This broadband switching matrix network is inventively characterized i that the main electrode of the other transistor that is connected opposite from the series circuit is continuously connected to a terminal of the operating voltage source.
In addition to providing the advantage of avoiding additional clock lines and, potentially, of being able to co-utilize the operating voltage supply of the cross-point-associated holding memory cell already required for the feed of the switching element controlled by this holding memory cell, the present invention provides the further advantage that the output line can be operated with a very small signal boost of, for example, 1 V for an operating voltage of, for example, 5 V
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I/O Systems 
