Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes

DETAILED DESCRIPTION What is claimed is: 1.
In a buffer memory device intermediate between a central processing unit and a main memory and operable to selectively memorize and read out an operand data block and an instruction data block in response to an operand request and an instruction request issued from said data processing unit, respectively, said buffer memory device comprising a cache memory having a plurality of cache areas each of which has a predetermined area size, the improvement wherein: said operand data block has an operand block size of said predetermined area size while said instruction data block has an instruction block size equal to N times said operand block size where N is an integer greater than unity; said buffer memory device comprising: producing means responsive to each of said operand and said instruction requests for producing an area address signal to access a single one and a plurality of the cache areas at said operand block size and at said instruction block size in response to said operand and said instruction requests, respectively, said area address signal being delivered to said cache memory; and cache memory monitoring means coupled to said producing means and said cache memory for monitoring said cache memory with reference to said area address signal.
2.
A buffer memory device as claimed in claim 1, the cache areas of said cache memory being loaded with said operand and said instruction data blocks, wherein said cache memory monitoring means comprises: block information storage means coupled to said producing means for storing a block information signal representative of which one of said operand and said instruction data blocks is stored in each of said cache areas to produce a stored block information signal in response to said area address signal; and detecting means responsive to said area address signal for detecting whether said stored block information signal is representative of said operand or said instruction data block to monitor said cache memory