Bus interface controller for computer graphics

DETAILED DESCRIPTION A bus interface controller for use in a digital information system having a system clock is disclosed.
The bus interface controller comprises more than four data channels of more than nine bits per channel which feed into apparatus for multiplexing the data channels bi-directionally so as to accomplish routing of data from any channel to any or all of the remaining channels.
It is one object of the invention to provide a bus interface controller having bi-directional I/O ports which alleviates board area and system bandwidth problems associated with prior art devices.
It is another object of the invention to provide a memory interface universally adaptable to many configurations in many digital systems, such as high speed graphics display systems.
It is yet another object of the invention to provide a device which may be embedded in a semiconductor material, such as gallium arsenide.
It is yet another object of the invention to provide a memory interface having bi-directional buses with less than a four nanosecond propagation delay through the system.
It is yet another object of the invention to provide a memory interface device having TTL/CMOS compatible inputs and outputs.
It is yet another object of the invention to provide a memory interface device having multiplexible buses.
These and further objects, advantages and features of the invention will become apparent through the drawings herein wherein like numerals refer to like elements and through the claims and description of the preferred embodiments contained herein.