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 Carrier detect circuit

Details
Inventors: Kanitz, Bruce R.; Jacobson, Charles L.;
Assignee: Xerox Corporation (Stamford, CT)
Primary Examiner: Yusko; Donald J.
Assistant Examiner:
Attorney, Agent or Firm:

A detector circuit utilizing two comparators, the first of which initially switches output at a first bias level, and the second of which switches output responsive to a preselected voltage on a capacitor. The voltage on the capacitor is controlled by the output of the first comparator which charges and discharges it through a dual time constant arrangement in order to sensitize the detector to activate a recorder after a preselected delay only upon receipt of a particularly shaped long duty cycle input signal. After receipt of the input signal, the bias level of the first comparator is changed so as to prevent switching until receipt of a second preselected input signal. In addition, after receipt of the first input signal, the time constant of charge-discharge arrangement for the capacitor is again altered.

DETAILED DESCRIPTION An object of the invention is to provide an improved carrier detect circuit of the type described in U.
S.
Pat.
No.
3,593,151 for preventing false startups of printing transducers in facsimile transceivers.
A further object of the invention is to provide a carrier detect circuit with an improved noise rejection capability for preventing false startups due to spurious noise at the facsimile receiver.
These and other objects of the invention are accomplished by a detector circuit utilizing two comparators, the first of which initially switches output at a first bias level, and the second of which switches output responsive to a preselected voltage on a capacitor.
The voltage on the capacitor is controlled by the output of the first comparator which charges and discharges it through a dual time constant arrangement in order to sensitize the detector to activate a recorder after a preselected delay only upon receipt of a particularly shaped long duty cycle input signal.
After receipt of the input signal, the bias level of the first comparator is changed so as to prevent switching until receipt of a second preselected input signal.
In addition, after receipt of the first input signal, the time constant of the charge-discharge arrangement for the capacitor is again altered.



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