Cell flow control in square-grid expanded ATM switch

DETAILED DESCRIPTION Therefore, an object of the present invention is to provide a backpressure-type cell flow control method and system to a square-grid expanded ATM switch achieving fair cell flow control between input port lines.
According to an aspect of the present invention, a flow control system in a square-grid expanded switch having an array of output buffer modules having a plurality of rows and columns, wherein one output port is associated with a plurality of output buffers each belonging to different rows and same column, the system includes: a backpressure controller provided in each of the output buffer modules for generating a backpressure control signal when an amount of data stored in an output buffer included in a corresponding output buffer module exceeds a predetermined threshold, to avoid an overflow of the output buffer; and a common backpressure generator provided in each of the output buffer modules, for generating a common backpressure control signal when a backpressure control signal is generated by at least one of backpressure controllers provided in output buffer modules belonging to a corresponding column and outputs the common backpressure control signal to a plurality of input buffers storing data to be forwarded to an output port associated with the output buffer.
According to another aspect of the present invention, in a square-grid expanded swatch comprising: M.
times.
N input ports, where M and N are integers; M.
times.
N output ports; M.
times.
N input modules corresponding to respective ones of the M.
times.
N input ports, each of the input modules including M.
times.
N input buffers corresponding to respective ones of the M.
times.
N output ports; an M.
times.
M array to output butter modules, wherein M rows of the array are associated with respective ones of M input port groups obtained by dividing the M.
times.
N input ports by N, M columns of the array are associated with respective ones of M output port groups obtained by dividing the M.
times.
N output ports by N, and each of the output buffer modules includes N output buffers, wherein each of the M