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| Asynchronous sample pulse generator |
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Circuit for designating instruction pointers for use by a processor decoder
| Details |
Inventors: Phillips, Christopher E.; Nemirovsky, Mario;
Assignee: National Semiconductor Corporation (Santa Clara, CA)
Primary Examiner: Eng; David Y.
Assistant Examiner: Patel; Gautam R.
Attorney, Agent or Firm: Limbach & Limbach L.L.P.
A circuit designates the values of an M bit first pointer and of an N+M bit second pointer. A first register circuit network holds the M bit first pointer, and a second register circuit network into holds an M bit portion of the N+M bit second pointer. A third register circuit network holds the remaining N bit portion of the N+M bit second pointer. A combiner circuit network, connected to receive the M bit first pointer from the first register circuit network, combines the received M bit first pointer with an externally provided data element length value to generate a new M bit first pointer. The combiner circuit network selectively generates a carry signal. The new M bit first pointer is selectively provided for loading into the first register circuit network and for loading into the second register circuit network as the M bit portion of the N+M bit portion of the second pointer. The remaining N bit portion of the N+M bit second pointer is received from the third register circuit network and, in response to the carry signal, one of the received remaining N bit portion and a modified remaining N bit portion is provided as a new remaining N bit portion for loading the new remaining N bit portion into the third register circuit network. |
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DETAILED DESCRIPTION FIG.
2 schematically illustrates an instruction pointer designation circuit 200 in accordance with the present invention.
A temporary instruction pointer ("TIP") register 102 holds a TIP value that points to an instruction (or portion of an instruction) in a line buffer, such as in the line buffer 100 (shown in FIG.
1).
The TIP register 102 is shown to have four bits, such that a TIP value contained within the TIP register 102 may point to any location in a sixteen (i.
e.
, 2.
sup.
4) location line buffer.
A demand instruction pointer ("DIP") value is collectively held within two registers, DIP.
sub.
-- L 104 and DIP.
sub.
-- H 106.
The DIP value always points to the beginning processor memory address of an instruction currently being decoded by a decoder (not shown).
In particular, DIP.
sub.
-- L register 104 holds the least significant four bits (0 through 3) of the beginning processor memory address of the instruction currently being decoded; and DIP.
sub.
-- H register 106 holds the most significant twenty-eight bits (4 through 31) of the beginning processor memory address of the instruction currently being decoded.
A first adder 108 has as its inputs the lengths of the various segments of the instruction currently being decoded, as determined by the decoder.
Thus, the minimum required size of the adder 108 is determined by the instruction segment lengths.
While the FIG.
2 embodiment 200 shows two segment lengths, Seg1.
sub.
-- len and Seg2.
sub.
-- len being input to the adder 108, the number of values to be input to the adder 108 in a particular embodiment of the present invention are dependent on the possible formats of the particular instructions being decoded.
The adder 108 adds together the lengths of the various segments to determine the total instruction length, Instr.
sub.
-- len, which is provided to the output of the adder 108.
Alternatively, one or more adders may be employed to accumulate the segment lengths of an instruction as the instruction is being decoded.
A second adder 110, which is a four bit adder, is connected to receive, first, the Instr
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I/O Systems 
