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Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer
| Details |
Inventors: Baber, Marc;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Robertson; David L.
Assistant Examiner: Kim; Matthew
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
A method of addressing an arbitrary global element stored within a first local memory associated with a first processing device is described for a distributed memory computers which includes a multiplicity of processing devices each having an associated base pointer or memory location and an associated memory, each of the local memories storing a subarray of a global array, each subarray having a subarray base element, each of the memories having a subarray base element memory address with said global array including a multiplicity of global elements. The method includes the steps of calculating subarray offsets for each subarray, calculating base pointer values for each processing device based upon its associated subarray offset, generating base pointer electrical values represented of a base pointer values, storing base pointer electrical signals within base pointer memory location, receiving an offset signal representative of the offset of the arbitrary global element, and generating address signals for the first local memory by combining the base pointer electrical signal for the first processing device with the arbitrary with element offset signals. Circuitry for addressing an arbitrary global element stored within a first local memory associated with a first processing device is also described in a context of the distributed memory computer having a multiplicity of processing devices, each one having a base pointer memory location and an associated memory, each of the memory storing a subarray of a global array and having a base element, each memory having a base element address and the global array including a multiplicity of global elements. |
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DETAILED DESCRIPTION OF INVENTION FIG.
2 illustrates in block diagram form a distributed memory computer 20, which implements the global addressing scheme of the present invention.
As will be described in more detail below, distributed memory computer 20 utilizes unique base pointers that allow a global addressing scheme to be used for both local and non-local data accesses.
Distributed memory computer 20 includes m central processing units (CPUs) 22a, 22b, 22c .
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22m, where m is an arbitrary number.
CPUs 22a, 22b, 22c .
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22m may be realized using any conventional microprocessor; Intel's 386, 486, or 860 microprocessors for example.
Each CPU 22a, 22b, 22c .
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22m has an associated local memory 24a, 24b, .
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24m.
Local memories 24a, 24b, .
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24m may be realized using any conventional semiconductor memory device.
For example, DRAMs, SRAMs, and ROMs would all be acceptable implementations.
Each local memory 24a, 24b, .
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24m may also be realized using multiple memory devices.
Each CPU 22a, 22b, .
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22m is directly connected to its associated local memory 24a, 24b, .
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24m.
Together each CPU and its associated local memory form a node 26a, 26b, .
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26m.
Nodes 26a, 26b, .
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26m communicate with each other via interconnection network 28.
Interconnection network 28 permits each CPU 22a, 22b, .
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22m to access data not stored within its associated local memory 24a, 24b, .
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24m.
In other words, interconnection network 28 facilitates non-local data accesses.
Interconnection network may facilitate non-local data accesses by keeping track of each local memory's base pointer or by keeping track of which node each array element is stored in.
Non-local data accesses are necessary because each CPU 22a, 22b, .
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22c potentially needs access to all data contained within global array 40, yet only a portion, or subarray 42a, 42b, .
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42m, of the global array 40 is stored within each local memory 24a, 24b, .
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24m.
The present invention increases the performance of distributed memory computer 20 by using a single global addressing scheme for both local and non-local data accesses
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