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Method for synchronizing interconnected digital equipment
Digital networks are represented as a combination of digital equipment shown as nodes in FIG. 1 interconnected by links shown as lines in FIG. 1. Sychronization ...
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Methodology for increasing the average run length produced by replacement selection strategy in a system consisting of multiple, independent memory buffers
In light of the foregoing, there is provided an external parallel sort method for use in a computer system having a plurality of record storage areas available for ...
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Method and apparatus for dispatching tasks requiring short-duration processor affinity
To achieve these and other objects, this invention provides a mechanism for efficiently redispatching a task from a first processor (lacking a required resource) to a ...
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Method of processing sub-images of an image field
What I claim is: 1. A method of image processing comprising the steps of: viewing an image field; dividing the image field into a plurality of sub-images; determining in ...
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Deadlock resolution with cache snooping
FIG. 1 is a block diagram of a data processing apparatus according to the present invention. It is characterized by a system bus 10 which is connected to a plurality of ...
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Dual port memory device with improved serial access scheme
OF THE DRAWINGS FIG. 1 is a schematic block diagram of a dual port memory according to a prior art; FIG. 2 is a timing diagram showing operation of the memory of FIG. 1;...
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Semiconductor memory device capable of relieving defective bits
Accordingly, an object of this invention is to provide a semiconductor memory device in which the leak current occurring in defective bits can be interrupted even if it ...
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Protection circuit for non-volatile memory
What is claimed is: 1. A protection circuit for a non-volatile memory comprising: means for developing an operating voltage for said memory; means for developing a reset ...
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Disk cache control unit
The object of the present invention is to provide a disk cache control unit which can reduce wasteful rotational delays on the disk unit side in the exchange of data ...
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Internally cached static random access memory architecture
The present invention, in its broadest form, is directed to a circuit for internally caching a memory device having a main memory. The circuit is comprised of a cache ...
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