Communication line driver, LSI for interface including such a circuit and communication terminal apparatus

DETAILED DESCRIPTION It is an object of the invention to provide a communication line driver which intends to a reduction of the number of externally attached components in an LSI form.
Another object of the invention is to provide a communication line driver which can reduce power consumption of an interface circuit including a communication line driver and which can easily form a one-chip LSI.
A communication line driver according to one feature of the invention comprises: a trimming circuit for adjusting a reference voltage generated by a reference voltage generating circuit; a driving device for driving a communication line to transmit a signal to the communication line; an internal power source buffer for applying a constant voltage to the driving device by a constant voltage control based on an output of the trimming circuit; a bias circuit for deciding an internal operating power source current of the internal power source buffer on the basis of the output of the trimming circuit; and a current limiter to limit the current which is supplied from the internal power source buffer to the driving device in an overload state in the communication line drive.
In this instance, the reference voltage generating circuit obtains the reference voltage by extracting a difference between a threshold value of a depletion type field effect transistor whose threshold value has been lowered by an ion implantation and a threshold value of a field effect transistor which is coupled so that a current that is equal to the current flowing to the depletion type field effect transistor flows by a current mirror circuit.
The trimming circuit can include feedback control means such as a fuse circuit for holding information to adjust an amplification factor of an operational amplifying circuit by controlling a negative feedback amount of the operational amplifying circuit for amplifying the output voltage of the reference voltage generating circuit.
The internal power source buffer includes a source follower of the field effect transistor provided as an output stage of the current which is supplied to the driving device and a field effect transistor which is connected to a drain electrode side of the above field effect transistor and forms the current limiter by limiting the current flowing to the field effect transistor