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Communications controller utilizing an external buffer memory with plural channels between a host and network interface operating independently for transferring packets between protocol layers
| Details |
Inventors: Tan, Min P.; Fuh, Eric; Chan, deceased, Philip; Ta, John;
Assignee: Standard Microsystems Corporation (Hauppauge, NY)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Kim; Sang Hui
Attorney, Agent or Firm: Hopgood, Calimafde, Kalil & Judlowe
A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout. |
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DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT Referring to FIG.
2, the programmable (VLSI) data communication controller chip 15 of the present invention, hereinafter "data communication controller" (DCC), is shown with its parallel I/O port 16 interfaced with the system bus 17 of host computer system 18.
As shown, host system 18 has a host processor 19, program memory 20B and system memory 20A.
In order to buffer transmit and receive packets and exchange between each other information such as protocol and configuration parameters, a randomly accessible shared buffer memory (e.
g.
RAM) is interfaced with system bus 17.
Also, a conventional communication medium interface device 22 is provided to interface between serial I/O port 23 of the data communication controller and communication medium 24.
For purposes of illustration, the communication network into which the data communication controller of the present invention is inserted, is a Token-Ring Network having a network communication protocol defined by the well known IEEE 802.
5 Standard.
For a detailed description of the Token-Ring configuration, formats and facilities used with this standard, see page 25-84 of "Information Technology Local and Metropolitan Area Networks--Part 5: Token Ring Access Method and Physical Layer Specifications" , Technical Committee on Computer Communications of the IEEE Computer Society, March 1992, published by The Institute of Electrical and Electronics Engineers, Inc.
While not schematically illustrated in FIG.
2, Eight Access-Class Transmit Queues, one MAC-Packet Receive Queue, and one Non-MAC Packet Receive Queue are managed in each station's shared buffer memory 21, using a software based low-level driver under the control of the host processor.
This particular queuing structure is necessitated by the IEEE 802.
5 Standard, and understandably will vary in relation to the communication network protocol utilized in each particular application.
As will be described in greater detail hereinafter, each station in the Token-Ring Network will have a data communication controller of the present invention, and each such controller incorporates a dedicated MAC CPU running the IEEE 802
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I/O Systems 
