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Compressed Instruction format for use in a VLIW processor
| Details |
Inventors: Jacobs, Eino; Ang, Michael;
Assignee: Philips Electronics North America Corporation (N.Y., NY)
Primary Examiner: Pan; Daniel H.
Assistant Examiner:
Attorney, Agent or Firm: Barschall; Anne E.
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.
1a shows the general structure of a processor according to the invention.
A microprocessor according to the invention includes a CPU 102, an instruction cache 103, and a data cache 105.
The CPU is connected to the caches by high bandwidth buses.
The microprocessor also contains a memory 104 where an instruction stream is stored.
The cache 103 is structured to have 512 bit double words.
The individual bytes in the words are addressable, but the bits are not.
Bytes are 8 bits long.
Preferably the double words are accessible as a single word in a single clock cycle.
The instruction stream is stored as instructions in a compressed format in accordance with the invention.
The compressed format is used both in the memory 104 and in the cache 103.
FIG.
1b shows more detail of the VLIW processor according to the invention.
The processor includes a multiport register file 150, a number of functional units 151, 152, 153, .
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, and an instruction issue register 152.
The multiport register file stores results from and operands for the functional units.
The instruction issue register includes a plurality of issue slots for containing operations to be commenced in a single clock cycle, in parallel, on the functional units 151, 152, 153, .
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A decompression unit 155, explained more fully below, converts the compressed instructions from the instruction cache 103 into a form usable by the IIR 154.
COMPRESSED INSTRUCTION FORMAT 1.
General Characteristics The preferred embodiment of the claimed instruction format is optimized for use in a VLIW machine having an instruction word which contains 5 issue slots.
The format has the following characteristics unaligned, variable length instructions; variable number of operations per instruction; 3 possible sizes of operations: 26, 34 or 42 bits (also called a 26/34/42 format).
the 32 most frequently used operations are encoded more compactly than the other operations; operations can be guarded or unguarded; operations are one of zeroary, unary, or binary, i
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I/O Systems 
