Compression/decompress with ECC data flow architecture

DETAILED DESCRIPTION The compression/decompression and ECC architecture of the present invention is set forth in FIG.
3.
Again, where like components correspond to like components in FIGS.
1 and 2, the same reference numerals are utilized.
In FIG.
3, it can be readily observed that the CD co-processor 62 and its corresponding CD RAM 64 are located externally from the host computer 10 in the peripheral adapter 60.
However, the ECC is performed in software internal to the host RAM 70.
Hence, the present invention reduces the hardware cost of FIG.
1 by approximately fifty percent by maintaining the CD co-processor and RAM 62 and 64 hardware on the peripheral adapter 60 thereby preserving significant compression/decompression speed while reducing the physical costs by placing the ECC as software in the host RAM 70.
Under the teachings of the present invention, the CD activity occurs external of the host computer and is located in the periphery whereas the ECC activity occurs internally in the host computer 10.
More importantly, only one CD processor and CD RAM is utilized under the teachings of the present invention.
One hardware implementation will service all of the peripheral devices even though the CD processor and CD RAM are located on one peripheral adapter card.
This significantly reduces expense since individual CD processors and CD RAMs are not required on individual peripheral adapters.
In operation, the application program file 31 corresponding to peripheral device 50 is loaded into the host RAM 70.
This includes loading the ECC program module 32 into the host RAM as the ECC RAM 76 and ECC program RAM 72.
The host computer 10 can now generally operate as follows.
First, data for a selected peripheral device is delivered from the application program data buffers in the host RAM over the data bus 22 of the I/O channel 20 and into the CD compressor 62 of the peripheral adapter 60.
Compression then occurs.
The compressed data is delivered on the I/O data bus 22 over the I/O channel 20 to the ECC RAM 76 in the host RAM 70