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| Method of processing sub-images of an image field |
| What I claim is: 1. A method of image processing comprising the steps of: viewing an image field; ... |
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| Deadlock resolution with cache snooping |
| FIG. 1 is a block diagram of a data processing apparatus according to the present invention. It is ... |
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| Dual port memory device with improved serial access scheme |
| OF THE DRAWINGS FIG. 1 is a schematic block diagram of a dual port memory according to a prior art;... |
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| Semiconductor memory device capable of relieving defective bits |
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| Protection circuit for non-volatile memory |
| What is claimed is: 1. A protection circuit for a non-volatile memory comprising: means for ... |
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| Disk cache control unit |
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| Internally cached static random access memory architecture |
| The present invention, in its broadest form, is directed to a circuit for internally caching a ... |
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| Radio communication receiving device detecting a frequency modulation preamble signal |
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Computer vision system based upon solid state image sensor
| Details |
Inventors: Friedman, Mark B.; Kiliany, Gary J.;
Assignee: Sentient Systems Technology, Inc. (Pittsburgh, PA)
Primary Examiner: Ng; Jin F.
Assistant Examiner: Brinich; Stephen
Attorney, Agent or Firm: Webb, Burden, Robinson & Webb
A system for computer vision in association with a computer comprises a solid state image sensor or optic ram, a lens, a clock circuit for sequentially addressing the image sensor, and an edge detect circuit for detecting edges in the output bit stream of the image sensor. The edge detect circuit generates an interrupt signal for application to the clock circuit to stop the clock from advancing the addresses and for application to the computer to signal it to read the column and row address currently generated by the clock circuit. |
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DETAILED DESCRIPTION This invention comprises a computer vision system in which the camera comprises a suitable lens, a solid state image sensor, and a unique hardware interface between the image sensor and the typical computer inputs comprising a data bus, an address bus and, possibly, interrupt and control buses.
The system also comprises a program stored in main memory of the computer.
A solid state image sensor is analogous to a random access memory device.
It comprises a two-dimensional array of light sensitive memory cells.
The cells are arranged in rows and columns.
Each cell is accessible for reading, writing and refreshing.
By writing to a cell the initial signal value on the cell can be established.
The signals held on the cells decay at a rate related to the intensity of the light thereon.
In the usual situation each cell includes a capacitor that holds a charge that bleeds away at a rate depending upon the light intensity.
The polarity of the charge may vary from device to device.
In any event, the entire array may be charged and then allowed to "soak" under the light image that the lens causes to fall thereupon.
("Soak" simply means the cells are not being refreshed or read and thus the signals upon the cells are allowed to decay.
) After the soak period the image sensor is read by accessing each cell and comparing the charge thereon to a threshold.
The output for a cell that has not decayed to the threshold is a signal level, say 1, that is indicative of a darker area of the image and the output from a cell that has decayed below the threshold is a signal level, say 0, that is indicative of a lighter area on the image.
If each cell in the array is sequentially accessed by row and column, the output of the image sensor during reading is a bit stream.
The hardware interface according to this invention generates row and column addressing signals for sequentially accessing the memory cells and processes the output bit stream to detect edges between darker and lighter areas of the image
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I/O Systems 
