Configuration pin emulation circuit for a field programmable gate array

DETAILED DESCRIPTION The subject invention is an apparatus and method for providing a pin-to-pin emulation of SRAM-based FPGAs that is transparent to the user.
The present invention may be implemented in any application specific integrated circuit (ASIC), e.
g.
, a full custom chip, a standard cell, or a gate array.
The field programmable gate array (FPGA), has two functional stages, namely a programmable or configurable stage which commences at power on, and an operational stage which commences after the FPGA has been configured.
The programmable stage may be further split into four states, namely initialization, configuration, start-up and reconfiguration.
The present invention comprises an emulator circuit for mimicking the initialization, configuration, start-up and reconfiguration states of the FPGA.
As a result, the emulator circuit of the present invention provides the user with a transparent migration from the FPGA to an ASIC.