Connection/disconnection control circuit for data lines between memory groups

DETAILED DESCRIPTION An object of the present invention is to provide a memory device which can realize low power consumption as well as large capacity and high-speed operation.
Another object of the invention is to provide a data transfer control which can reduce the power consumption of a memory device that has a large capacity and operates at high speed.
According to the invention, the data input/output lines for two memory groups are connected to each other only when data transfer is performed between the two memory groups, and are disconnected in other cases.
A memory system according to the invention comprises a plurality of memory groups each having a plurality of memory cells, and a data line provided for each of the plurality of memory groups and commonly connected to the input/output terminals of the memory cells.
A memory controller performs data input/output control for all of the memory cells.
A data line division circuit performs electrical connection and disconnection between the data lines of arbitrary two adjacent memory groups of the plurality of memory groups.
Monitoring the data input/output control by the memory controller, a data transfer control circuit switches the data line division circuit to a connection mode only when data transfer is performed between the two adjacent memory groups.
Preferably, the data line division circuit is provided with a gate circuit for each data transfer direction.
These gate circuits are capable of connecting the data lines bi-directionally or only in the data transfer direction in accordance with a transfer control signal sent from the data transfer control circuit.
It is preferable that a prescribed single bit of the address to be used for data input/output control have a prescribed logical value for discriminating between the two adjacent memory groups.
The data transfer control circuit detects a data transfer between memory groups by monitoring the prescribed bit.
That is, the data transfer control circuit monitors at least the prescribed bit of the address, and detects, based on the detected prescribed bit value, whether data transfer is performed between the two adjacent memory groups or not