Control circuitry for data transfer in an advanced data link controller

DETAILED DESCRIPTION The increased use of Bit-Oriented-Protocols has resulted in a need for a low-cost, high speed LSI chip that can accommodate the three major BOP protocols.
It is also an object of the present invention to provide a data link controller having control means for controlling a multi-byte FIFO register in its transmitter and receiver sections for providing high data transfer rate.
These and other objects of the invention are achieved in accordance with a preferred embodiment of the invention by providing an advanced data link controller (ADLC) in LSI form on a single chip implemented in MOS technology and comprising an eight-bit data bus interface for communicating address, control, and data information between the ADLC and a microcomputer or terminal; four eight-bit control registers; two eight-bit prioritizable status registers; chip select circuitry; a transmitter section comprising control means for a three-byte FIFO register, zero insertion circuitry, frame check sequence generator, and flag/abort generator, for transmitting such information in serial form byte by byte on each transition of a clock signal to a communications link; and a receiver section comprising control means for a three-byte FIFO register, zero deletion circuitry, frame check sequence checker, flag/abort/idle detection circuitry; and loop control circuitry for receiving such information in serial form from byte by byte on each transition of a clock signal a communications link.