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Control of data access to memory for improved video system
| Details |
Inventors: Novak, Mark F.; Guttag, Karl M.; Redwine, Donald J.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Moffitt; James W.
Assistant Examiner:
Attorney, Agent or Firm: Graham; John G., Anderson; Rodney M.
In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof. |
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DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT Referring to FIG.
1, there may be seen a simplified representation of the components of a computer video system which employs a dual-port bit-mapped memory arrangement according to one embodiment of the invention.
More particularly, there may be seen a video display section 1 having a conventional raster-scanned CRT tube responsive to a video signal input 2 consisting of serial bits of data arriving at a rate of about 20 MHz or greater.
The standard TV signal normally provides 60 data frames per second, with 512 interlaced lines per frame, and each such line may have several hundred dots or pixel.
The product of these numbers indicates that data bits must be supplied to the CRT at frequencies of the order of 20 MHz.
For a simple black and white picture, each dot or pixel can be defined by one data bit, but up to four bits may be required for images in a more realistic sixteen shades of gray.
A full-color image may require three or four streams or planes of data and usually will require at least one byte (8-bits) per pixel.
The horizontal and vertical scanning and synchronizing circuitry 3 and video signal shaping circuitry 4 may be of a conventional design, and are not a functional part of the present invention.
In addition, the circuitry depicted in FIG.
1 may also include a complete TV monitor or receiver as needed.
However, the video data on input 2 is preferably received from a bit-mapped video memory 5 as will be described later herein, and this memory 5 will preferably have at least one cell for each corresponding pixel on the video screen 1.
The memory 5 may conveniently have a "parallel" or random input/output port 6, or it may have separate parallel input and output ports, in addition to the serial input port 2a and serial output port 2b depicted in FIG.
1.
In addition, port 6 is preferably coupled to a multiplexed address/data input/output bus 7 of a suitable microcomputer or microprocessor 8.
Referring again to FIG.
1, it will be noted that the memory 5 receives addresses appearing on the bus 7, to define the address for the serial ports 2a and 2b, and also to define addresses for writing into or reading from the memory 5, by way of the parallel or random port 6
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I/O Systems 
