Coordinate rotation digital computer processor (cordic processor) for vector rotations in carry-save architecture

DETAILED DESCRIPTION The object of the present invention is to provide a CORDIC processor that is constructed of simple elementary cells, can be easily modified in view of accuracy and word width and mainly represents a good compromise between low chip surface and high data rate.
The above object is achieved, according to the present invention, by the provision of a CORDIC processor for vector rotations constructed in accordance with a carry-save architecture for solving problems of real-time processing, in which the processor comprises (a) a vector path and an angle path whereby the vector path is composed of a plurality of series-connected vector iteration stages and the angle path is composed of a plurality of series-connected angle iteration stages; (b) a plurality of devices for mutual decoupling of the vector iteration stages and a plurality of devices for mutual decoupling of the angle iteration stages in order to enable a processing according to a conveyor belt principle known as pipelining; (c) a plurality of vector iteration stages and a plurality of angle iteration stages that contain addition/subtraction circuits, wherein, within a clock interval, only incomplete addition/subtraction operations occur and intermediate results at the end of the clock interval in the form of a carry word and of a sum word (carry-save number) are available on separate lines for carry and sum bits at the output of each vector and angle iteration stage, these words being available for further processing; (d) the plurality of vector iteration stages and the plurality of angle iteration stages comprising structure for realizing shift operations (multiplication with powers of 2) that allow a shift of carry and sum bits; (e) the plurality of angle iteration stages having sign detectors that employ the carry and sum bits for sign detection; (f) a multiplier that is connected to the output lines for the carry and sum words of a last vector iteration stage of the series for multiplying both the carry word and the sum word of each vector component by a correction factor; and (g) an adder that is connected to the output lines for the carry and sum words of a multiplier circuit that adds up the carry and sum words of both vector components to form components of a result vector