 Semiconductor memory device capable of relieving defective bits |
| Accordingly, an object of this invention is to provide a semiconductor memory device in which the ... |
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| Protection circuit for non-volatile memory |
| What is claimed is: 1. A protection circuit for a non-volatile memory comprising: means for ... |
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| Disk cache control unit |
| The object of the present invention is to provide a disk cache control unit which can reduce ... |
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| Internally cached static random access memory architecture |
| The present invention, in its broadest form, is directed to a circuit for internally caching a ... |
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| Radio communication receiving device detecting a frequency modulation preamble signal |
| The object of the present invention is to provide a radio communication receiving device that has a ... |
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| Memory access address comparison |
| It is an aim of embodiments of the present invention to provide write protection circuitry which ... |
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| Color television picture display device having a flicker reduction circuit |
| What is claimed is: 1. A color television picture display device comprising an analog-to-digital ... |
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| Line camera for imaging object strips on photosensitive detector lines |
| What is claimed: 1. A line camera for imaging object strips on photosensitive detector lines, ... |
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| Method for encoding SNMP summary objects |
| OF THE PREFERRED EMBODIMENT Referring to the drawings, especially FIG. 1, a concentrator 10 ... |
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| Apparatus and method for modifying signals from a CPU to a memory card |
| A computer system and method of operation is provided wherein the memory controller of the system ... |
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Cyclic data communication system
| Details |
Inventors: Ohkura, Yoshinori; Hamada, Takuji; Inada, Shunji; Yamaguchi, Shinichiro; Tomizawa, Hiroshi;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Lim; Krisna
Assistant Examiner:
Attorney, Agent or Firm: Kenyon & Kenyon
A data communication system carries out transmission and reception of periodic data between a plurality of computers, and especially an improved data communication system which aims at more effective utilization of a system bus in each computer and which also aims at more effective utilization of a data transmission channel transmitting periodic data, so that the load imposed on the system bus during transfer of periodic data in each computer can be minimized, and the rate of occupation of the data transmission channel during transmission and reception of periodic data can also be minimized. |
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DETAILED DESCRIPTION It is an object of the present invention to provide a data communication system which is advantageous in that the load imposed on a system bus during transfer of periodic data in each of a plurality of computers can be reduced, and the rate of occupation of a data transmission channel during transmission and reception of periodic data can also be reduced.
According to one of the features of the present invention, there is provided a data communication system comprising a data transmission channel, and a plurality of control computers connected to the data transmission channel through communication controllers respectively, wherein data held in one of the plural computers is transferred to the own communication controller in a data rewrite period and is then compared in the communication controller with the data transferred already onto the data transmission channel in the preceding data rewrite period, and, when the value of the data transferred now is detected to change from that of the preceding data, the data is transferred onto the data transmission channel.
According to another feature of the present invention, there is provided a data communication system which comprises a plurality of control computers coupled to a data transmission channel, each of the control computers including at least one CPU, a main memory, a system bus connected to the CPU and the main memory, and a communication controller connected between the system bus and the data transmission channel and having built-in data transmission and reception control circuits and a built-in memory for storing periodic data and in which periodically acquired periodic data is transmitted and received between the plural control computers through the data transmission channel, and each of the CPU's uses the periodic data stored in the main memory for executing required date processing, wherein each of the communication controllers receives the periodic data required at least for the own control computer and stores the received periodic data in the main memory, and means is provided for reading out rewritten periodic data only among those stored in the main memory to be transmitted and transmits the read-out periodic data onto the data transmission channel
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I/O Systems 
