DC-to-DC converter functioning in a pulse-skipping mode with low power consumption and PWM inhibit

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment (by way of example, and not of limitation), in which: A partial block diagram of a stepdown DC-to-DC converter (commonly known as "buck" converter) controlled in a current mode by a PWM control loop, is depicted in FIG.
1.
In order to avoid overburdening the figures, the circuit of the current mode PWM control loop has been omitted from the block diagram of FIG.
1 by schematically representing it by a PWM comparator suitable to output a turn-off signal for the switch of the converter.
Of course, the whole PWM control loop will normally comprise an error amplifier and an amplifier of the voltage present across the sensing resistance (Rsens) for monitoring the current that flows through the inductor L of the power circuit of the converter.
The power circuit of the converter further comprises a switch, represented in the shown sample by a power MOS transistor (MOS switch), a discharge diode (FW diode) and an output storage capacitor (C).
Of course, a typical PWM control circuit of the state of the power switch of the converter may also comprise a timing clock circuit (which may be substituted by a local oscillator), a driving flip-flop of the switch of the converter, as represented in the scheme of FIG.
1 by the cross-coupled pair of NOR circuits G4 and G3, as well as the driving buffer stages I and A.
The block diagram of FIG.
1 evidences the elements that implement the method of the invention for minimizing switching losses during an idling phase of operation (idle mode of operation) of the converter.
These elements are represented by the offset comparator COMP and by the logic circuits G1, G2, G5 and G6.
Typically, the current mode PWM control system, symbolically represented in the figure by the comparator PWM, outputs a logic signal which normally forces the turning off of the switch of the converter when the signal is at a logic "1" while permitting the turning on of the switch by the clock signal when at a logic "0"