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Details
Inventors: Trevett, Neil F.; Neave, John W.;
Assignee: 3Dlabs Ltd. (Egham, GB)
Primary Examiner: Swann; Tod R.
Assistant Examiner: Asta; Frank J.
Attorney, Agent or Firm: Groover; Robert, Formby; Betty

A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described, by way of a non-limiting example, with reference to the drawings, in which FIGS.
4, 8, 9, 22 to 24 and 48 are of major relevance to the present invention.
Hardware Overview FIGS.
1 to 3 show three different hardware configurations of computer systems embodying the invention.
Referring firstly to FIG.
1, a host computer 10 has its own backplane in the form of a VME bus 12 which provides general purpose communications between various circuit boards of the computer, such as processor, memory and disk controller boards.
To this known configuration, and within a standard housing 14 for the computer 10, there is added a board on which is provided a renderer 16 and a video processor 18, a Futurebus+ 20, and a front-end board 22.
The renderer 16 is connected to the VME bus 12 and the Futurebus+ 20, and also communicates with the video processor 18, which in turn drives an external color monitor 24 having a high-resolution of, for example 1280.
times.
1024 pixels.
The front-end board 22 is also connected to the Futurebus+ 20 and can communicate with a selection of peripherals, which are illustrated collectively by the block 26.
The configuration of FIG.
1 is of use when the host computer 10 has a VME backplane 12 and there is sufficient room in the computer housing 14 for the renderer 16, video processor 18, Futurebus+ 20 and front-end board 22, and may be used, for example, with a `Sun Workstation`.
In the case where the computer housing 14 is physically too small, or where the host computer 10 does not have a VME or Futurebus+ backplane, the configuration of FIG.
2 may be employed.
In FIG.
2, a separate housing 28 is used for the renderer 16, video processor 18, front-end board 22 and Futurebus+ 20, as described above, together with a VME bus 12 and a remote interface 30.
In the host computer housing 14, a host interface 32 is connected to the backplane 34 of the host computer 10, which may be of VME, Qbus, Sbus, Multibus II, MCA, PC/AT, etc



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