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| Arbitration circuitry for deciding access requests from a multiplicity of components |
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| Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system |
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| Multiplexing communication card and scanning method for run-in testing |
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Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings
| Details |
Inventors: Okamoto, Toshiya;
Assignee: Sharp Kabushiki Kaisha (Osaka, JP)
Primary Examiner: Chan; Eddie P.
Assistant Examiner: Kim; Hong C.
Attorney, Agent or Firm:
The system includes a data driven processor, a main memory, a cache memory and a memory access unit for accessing the cache memory, the main memory or both and for maintaining the contents of the cache memory in coherence with the contents of the main memory. Read/write from and to the memory can be carried out accurately at high speed without increasing the circuit scale. The memory access unit stores, in response to a write instruction, the data also in the cache memory. Even in a specific processing in which one data is read only once, the data can be read from the cache memory unit. Preferably, the memory access unit stores information specifying an access mode of the most recent access to the cache memory address by address, and compares the most recent access mode and the mode of the access to be taken. The memory access unit permits or inhibits access based on the result of comparison. A data item is not likely to be erroneously overwritten by the subsequent data before it is read. Preferably, the system includes main memories to which different addresses are allotted. The memory access unit accesses the cache memory by converting the address such that areas of different main memories are commonly assigned to one same area of the cache memory. For example, a part of the address is masked. Since a common area can be used both for reading and writing, the circuit scale can be reduced. A method for efficiently operating the system is also disclosed. |
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DETAILED DESCRIPTION Therefore, an object of the present invention is to provide a data driven information processing system allowing accurate read/write from and to the memory at high speed without increasing the circuit scale.
Another object of the present invention is to provide a data driven information processing system particularly suitable for executing a specific processing, allowing accurate read/write from and to the memory at high speed without increasing the circuit scale.
A still another object of the present invention is to provide a data driven information processing system including a plurality of data driven processors, allowing accurate read/write from and to the memory at high speed without increasing the circuit scale.
A still further aspect of the present invention is to provide a data driven information processing system including a plurality of data driven processors, allowing precise read/write from and to the memory at high speed by the plurality of processors, without increasing the circuit scale.
A still further object of the present invention is to provide a data driven information processing system including a plurality of data driven processors and a plurality of main memories, allowing write to the main memory by a processor and read from the memory by another processor accurately at high speed without increasing the circuit scale.
The data driven information processing system of the present invention includes a data driven processor; a main memory for storing data to be processed by the data driven processor; a cache memory unit provided between the data driven processor and the main memory for storing at least a part of the contents of the main memory, which can be accessed faster than the main memory; and a memory access unit connected to the data driven processor, the cache memory device and the main memory, responsive to an issuance of an access instruction to the main memory by the data driven processor for accessing the cache memory unit, the main memory or both for inputting/outputting data between the data driven processor and the main memory or the cache memory unit and for maintaining the cache memory unit such that the contents in the cache memory unit are in coherence with the contents of the main memory
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