Data link processor for magnetic tape data transfer system

DETAILED DESCRIPTION What is claimed is: 1.
A peripheral-controller for operation in a system which includes a main host computer and a plurality of magnetic tape transport units, said peripheral controller is housed in a base module which provides distribution control circuitry to connect and disconnect peripheral controllers to said main host computer and maintenance circuitry to test the operation of such peripheral-controllers, said peripheral-controller comprising: (a) common control circuit means including: (a1) control store means for storing micro-code word operators, each of said word operators being separately addressable and selected by control data from a peripheral dependent circuit means; (a2) means connected to generate a current-address to said control store means to select a first micro-code word operator, said generation means receiving control data from said peripheral dependent circuit means; (a3) means to generate the next forthcoming micro-code word operator; (a4) stack register means to temporarily hold the current address of said first micro-code word operator; (a5) latching register means to temporarily store and convey said micro-word operator to said peripheral dependent circuit means for execution of said operator; (a6) connection means to signal access-requests to said host computer; (a7) bus means to receive data from and to transmit data to said main host computer; (a8) additional bus means to receive data from and to transmit data to selected magnetic tape transport units; (a9) RAM buffer means to temporarily store data being transferred between a selected magnetic tape transport unit and said host computer said buffer means being controlled by signals from said peripheral dependent circuit means; (b) said peripheral dependent circuit means including: (b1) bi-directional data path means to a selected magnetic transport unit; (b2) address logic means for formulating addresses for the read-out and write-in of data in said RAM buffer means; (b3) multiplexor means for selecting a source of data that is to be transmitted to said RAM buffer means; (b4) means to set a unique address to identify said peripheral dependent circuit means; (b5) word generation shift register means to provide control and information data to said host computer and to a selected magnetic tape transport unit; (b6) logic means for executing micro-code word operators received from said latching register means