 Memory device with multiple internal banks and staggered command execution |
| According to the present invention, a memory device has an array of memory cells arranged in a ... |
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| Synchronous semiconductor memory device operable in a plurality of data write operation modes |
| An object of the invention is to provide an SDRAM which allows easy adjustment of an internal data ... |
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| Latched type clock synchronizer with additional 180.degree.-phase shift clock |
| An object of this invention is to provide an internal clock circuit in an integrated circuit that ... |
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| Programmable bit line drive modes for memory arrays |
| Accordingly, it is an object of the present invention to provide an improved memory array. It is a ... |
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| Serial bus interface capable of transferring data in different formats |
| Accordingly, it is an object of the present invention to provide a serial bus interface which has ... |
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| Data transmitting method |
| It is a primary object of the invention to solve the above problems and present a faster data ... |
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| Self timed interface |
| An object of this invention is the provision of a cost effective bus data transfer system that can ... |
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| Digital phase-lock loop control system |
| It is an object of this invention to implement a PLL function. It is also an object of this ... |
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| Data output buffer of a semiconducter memory device |
| It is therefore object of the present invention to provide a semiconductor memory device capable of ... |
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| Synchronous DRAM having a high data transfer rate |
| Accordingly, it is an object of the present invention to provide a semiconductor memory which has ... |
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Data output buffer control circuit of a synchronous semiconductor memory device
| Details |
Inventors: Yoo, Hak-Soo; Won, Jong-Hak;
Assignee: Samsung Electronics Co., Ltd. (Suwon, KR)
Primary Examiner: Dinh; Son T.
Assistant Examiner: Mai; Son
Attorney, Agent or Firm: Marger, Johnson, McCollom & Stolowitz, P.C.
A method of controlling the buffering of output data by synchronizing with an external system clock, including the steps of generating an internal clock pulse, transferring data from a chip to a pair of data output lines in response to the internal clock pulse, generating an output mode control signal in synchronism with the internal clock pulse, gating the output mode control signal from the first edge of the internal clock pulse to the first edge of the next internal clock pulse to produce an output control signal, and driving data output to an output pad in response to the output control signal is disclosed. A data output buffer control apparatus of a synchronous semiconductor memory device operating in synchronism with an externally applied system clock pulse is also disclosed, which apparatus has an internal clock pulse generator for generating an internal clock pulse in response to the system clock pulse, an output register for transmitting data from the inside of the chip to a pair of data output lines in synchronism with the first edge of the system clock pulse, an output mode control signal generator for generating a predetermined output mode control signal in synchronism with the system clock pulse, an output buffer control means for gating the output mode control signal from the first edge to the second edge of an internal clock pulse to create an output control signal, and a data output means for driving the output of the output register in response to the output control signal of the output buffer control means. |
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DETAILED DESCRIPTION It is, therefore, an object of the present invention to enable a data output buffer control apparatus of a synchronous semiconductor memory device to operate in synchronism with an externally supplied system clock pulse to produce high speed data transfer.
It is another object of the present invention to enable a data output buffer control apparatus that allows changing of the output cycle of the output buffer of a synchronous semiconductor memory device, thereby enabling control of the duration of the output cycle.
According to the present invention, a data output buffer control apparatus of a synchronous semiconductor memory device operating in synchronism with an externally applied system clock pulse comprises an output register for transmitting data from the inside of the chip to a pair of data output lines in synchronism with the first edge of the system clock pulse, an output mode control signal generator for generating a predetermined output mode control signal in synchronism with said system clock pulse, an output buffer control means for gating said output mode control signal from the first edge to the second edge of said internal clock pulse, and a data output means for driving the output of said output register in response to the output signals of said output buffer control means.
The present invention will now be described more specifically with reference to the drawings attached, the description being by way of example only and not of limitation.
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I/O Systems 
