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| Asynchronous digital time-division multiplexing system with distributed bus |
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Data processing device having an expandable address space
| Details |
Inventors: Mitsuishi, Naoki; Baba, Shiro; Nagayama, Hiromi; Hayashi, Tsutomu; Hayakawa, Yukihide;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Harvey; Jack B.
Assistant Examiner: Seto; Jeffrey K.
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information. |
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DETAILED DESCRIPTION In the aforementioned CPU, however, the address register has a length of 16 bits, and the memory to be referred to by the CPU has a capacity of 65,536 bytes (=2.
sup.
16 or 64 Kbytes).
In the application of the on-chip control using the 8-bit single-chip microcomputer, on the other hand, the high performance of a device requires large-capacity programs or data to be handled.
At this time, moreover, the function is desired to have an upper compatibility with the aforementioned conventional CPU.
In other words, the user can desirably utilize the source programs or object programs which are already developed for the conventional CPU, wholly or partially as they are.
If either the peripheral function of the microcomputer or the portion depending upon an application system is then modified, the software or the application system can be promptly developed for a shortened time period.
For these demands, we have investigated a CPU which can refer to a memory of 64 Kbytes or more while reducing the logical/physical scales of the aforementioned CPU and realizing a relatively high processing performance at a relatively low manufacture cost.
On the contrary, the single-chip microcomputer, which is enabled to refer to a memory of 16,777,216 bytes (=2.
sup.
24 or 6 Mbytes) by adding a page register of 8 bits to the 8-bit CPU and combining it with the 16-bit register to generate addresses, is exemplified by H8/532 HD6475328 HD6435328 Hardware Manual Hitachi Ltd.
, published December 1988, the Engilish version of which correspondes to Hitachi Single-Chip Microcomputer H8/532 HD6475828 and HD6485828, Hardware Manual, 1st Edition, August 1989.
According to this memory referring method, the page register and the address register are absolutely independent of each other so that the method of realizing the hardware can be simplified.
On the other hand, neither the carry nor the borrow is transferred between the page register and the address register so that care should be always taken to prevent a series of programs or data from trespassing across the page boundary, in case the program or compiler is to be made
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I/O Systems 
