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| Control of data access to memory for improved video system |
| OF SPECIFIC EMBODIMENT Referring to FIG. 1, there may be seen a simplified representation of the ... |
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| Font cartridge adapter |
| OF PREFERRED EMBODIMENTS Referring to the FIG. 1, this invention mainly comprises the front shell 1... |
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| Document processing system |
| The present invention has been made in view of the above circumstances. It is an object of the ... |
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| Microprocessor based radiosonde |
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| Method and apparatus for encoding binary data |
| An object of the present invention is to provide a method and an apparatus for encoding binary data ... |
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| Serial data communication system having simplex/duplex interface |
| OF THE PREFERRED EMBODIMENT System Overview Machine Description Master/Area Communication System MA... |
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| Detecting improper operation of a digital data processing apparatus |
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| "Simple code" encoder/decoder |
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Data processing system having a unique address translation unit
| Details |
Inventors: Wallach, Steven; Holberger, Kenneth D.; Staudaner, Steven M.; Henry, Carl;
Assignee: Data General Corporation (Westboro, MA)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:
A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit. |
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DETAILED DESCRIPTION What is claimed is: 1.
In a data processing system which operates in first and second operating modes, said system responding in said first operating mode to first logical addresses containing a first number of address bits and responding in said second operating mode to second logical addresses containing a second number of address bits, said system comprising: memory means responding to physical addresses containing said second number of address bits; program counter means for providing logical addresses for accessing a sequence of instruction words a first plurality of said instruction words, during said first operating mode, being accessed from said memory using said first logical addresses and a second plurality of said instruction words, during said second operating mode, being accessed from said memory means using said second logical addresses; decode means, responsive to instruction words obtained from said memory means, for decoding said instruction words, the decoding thereof producing address descriptor bits, one or more selected ones of said address descriptor bits signifying whether first or second logical addresses are to be used for accessing a subsequent instruction word; means connected to said decode means and responsive to said address descriptor bits when said first logical addresses from said program counter means are so signified for converting said first logical addresses into logical addresses containing said second number of address bits; and means responsive either to said converted logical addresses from said program counter means for translating said converted logical addresses or said second logical addresses into physical addresses containing said second number of address bits for supply to said memory means.
2.
A system in accordance with claim 1 wherein said first logical addreses have fewer bits than said second logical addresses.
3.
A system in accordance with claim 2 wherein said first logical addresses are logical word addresses which have fifteen bits and said second logical addresses are logical word addresses which have thirty-one bits
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