 Gate array with bidirectional symmetry |
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| Multiprocessor systems having distributed shared resources and deadlock prevention |
| FIG. 1 shows in block diagram a multiprocessor system in accordance with the present invention. T... |
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| Apparatus and method for providing a transparent disk drive back-up |
| OF THE PREFERRED EMBODIMENT Having summarized various aspects of the present invention, reference ... |
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| Method for preventing unauthorized modification of data in a device with a nonvolatile memory |
| It is accordingly an object of the invention to provide a method for preventing unauthorized data ... |
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| Method of reading digital data on magnetic tape |
| I have hereby invented how to read digital data written in the standard format on a magnetic tape, ... |
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| Method and apparatus for synchronizing disk drive requests within a disk array |
| There is provided, in accordance with the present invention, a method and apparatus for generating ... |
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Data processing system having interlinked slow and fast memory means
| Details |
Inventors: Brantingham, George L.; Someshwar, Ashok H.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Zache; Raulfe B.
Assistant Examiner:
Attorney, Agent or Firm: Grossman; Rene' E., Heiting; Leo N., Sharp; Melvin
A data processing system having a large slow main memory and having a small fast memory is disclosed with means for allowing slow memory calls to fast memory routines and means for allowing returns from programs executing in the fast memory so as to return to program execution in the slow main memory. Also disclosed is circuitry for selectively deactivating the main memory and for selectively activating the fast memory responsive to particular ones of data signals output from the main memory, and means for selectively deactivating the fast memory and for selectively deactivating the main memory responsive to predefined ones of data signals output from the fast memory, thereby allowing program calls embedded in the slow main memory to transfer execution control to the fast memory, and providing retransfer of execution control from the fast memory to the slow main memory in response to a RETURN code embedded in the fast memory. Thus, memory size and speeds may be selectively ratioed to obtain higher overall data processing system throughput. |
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DETAILED DESCRIPTION In accordance with the present invention, there is provided a data processing system having a large capacity first read only memory having a first access time, and a second read only memory, faster and of smaller capacity than the first read only memory, the second memory having a much faster access time than the first read only memory.
The second faster read only memory is utilized to store critical routines, such as arithmetic register operations, thereby making possible the operation of the central data processing unit at speeds limited only by the random logic capabilities of the processor unit.
The ratio of fast to slow read only memory operation may be adjusted for semiconductor area consumption versus speed of operation trade offs, and in the preferred embodiment is a 3 to 1 ratio.
The interaction of the fast read only memory (second memory) and slow read only memory (first memory) may be interlinked in any of several ways, such as in the preferred embodiment wherein the fast read only memory is activated in response to a specially formatted call instruction code data pattern being output from the slower ROM (first memory) and is deactivated in response to a return instruction signal pattern as output from the fast ROM (second memory).
This architecture alleviates the speed requirements on the main read only memory (first memory) by utilizing a relatively small fast read only memory (second memory), thereby allowing each of the first and second memory means to be optimized in size and speed for its prime function.
In the preferred embodiment, the main read only memory (first memory) is a very dense serial read only memory device which is relatively slow, and the fast read only memory (second means) has a significantly larger bit size than the slow read only memory, but has a much shorter access time.
This invention may be better understood by reference to FIG.
9L.
Illustrated is a means (1230 and 1250) for providing an address signal.
The means for providing an address signal may be comprised of latch means, register means from a processor, counter means, or other storage or counting circuitry
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I/O Systems 
