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Data-processor-having-wait-state-control-unit

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Data processor having wait state control unit

Details

Inventors: Yoshimatsu, Norifumi;
Assignee: NEC Corporation (Tokyo, JP)
Primary Examiner: Fleming; Michael R.
Assistant Examiner: Auve; Glenn A.
Attorney, Agent or Firm: Whitham & Marhoefer

A data processor (1) includes a wait state control unit (6) for generating a ready signal for instructing a bus control unit (3) to insert a wait state into a bus cycle being performed. The bus control unit performs a bus cycle with first and second states (T1 and T2). The wait state control unit includes a bus cycle judgement circuit, a register, a wait cycle selector/decoder, a wait cycle presence/absence detector for detecting whether or not a wait state is to be inserted into the bus cycle, and a ready signal generator for generating a ready signal in response to the detection signal from the wait cycle presence/absence detector for generating the ready signal in response to the detection signal irrespective of the absence of the decoded wait cycle number from the wait cycle selector/decoder. Thus, the wait cycle presence/absence detector, which detects only the requirement of the insertion of a wait state, causes the ready signal to be generated to the bus control unit even though the number of wait states has not been decoded by the end of the second state.

DETAILED DESCRIPTION Therefore, an object of the present invention is to provide a data processor having an improved wait state control circuit.
Another object of the present invention is to provide a wait state control unit which does not present the constraint on the enhancement in operation speed of a data processor.
A data processor according to the present invention includes a wait state control unit for generating a ready signal for instructing the insertion of a wait state into a bus cycle being currently performed, which unit comprises a bus cycle judgement circuit for judging the bus cycle being currently performed to produce judged bus cycle information, a register for storing a plurality of wait cycle numbers, a wait cycle selector/decoder for selecting one of the wait cycle numbers and decoding the selected wait cycle number to produce a decoded wait cycle number to be inserted, a wait cycle presence/absence detector supplied with the selected wait cycle number for detecting whether or not a wait state is to be inserted into the bus cycle being currently performed to produce a detection signal when the wait state is detected to be inserted, and a ready signal generator coupled to the wait cycle selector/decoder and the wait cycle presence/absence detector for generating the ready signal in response to the detection signal from the wait cycle presence/absence detector irrespective of the absence of the decoded wait cycle number from the wait cycle selector/decoder and continuing to generate the ready signal until the wait state is inserted into the bus cycle being currently performed by a number designated by the decoded wait cycle number.
The present invention pays attention to a fact that the wait cycle selector/decoder requires a relatively long time to decode the selected wait cycle number.
Therefore, the wait cycle presence/absence detector is provided to detect whether or not the wait state is required to be inserted into the current bus cycle.
Since this detector detects only the necessity of the insertion of the wait state, the detecting operation thereof is completed for a very short time

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