Data processor with on-chip logical addressing and off-chip physical addressing

DETAILED DESCRIPTION An object of the present invention is to provide a data processor which can reduce conflict during access of an instruction control unit and an instruction execution unit to a main memory so as to process instructions at a high speed.
The data processor of the present invention enables parallel operation of the instruction control unit 3 and the instruction execution unit 4 to effect pipeline control.
In order to eliminate the above-specified defects, according to the present invention, the instruction control unit and the instruction execution unit are equipped with associative memories, and first access the corresponding associative memory so that they do not use common address lines and data lines, before data are present, to access the main memory.
Namely the instruction control unit has a first associative memory storing instructions read out from the main memory, and an instruction controller which reads out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory.
The instruction execution unit has a second associative memory storing operand data read out from the main memory, and an instruction executer for executing the instruction by using operand data read out from the second associative memory when operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
As a result, no conflict arises between the instruction control unit and the instruction execution unit when data are present in the associative memory of at least one of the two memories.
This reduces the chance of one of the units being held on standby.
As a result, the instructions can be processed more rapidly.