Deadlock resolution with cache snooping

DETAILED DESCRIPTION FIG.
1 is a block diagram of a data processing apparatus according to the present invention.
It is characterized by a system bus 10 which is connected to a plurality of system resources.
One such system resource is illustrated in FIG.
1.
The one system resource includes a local processor 11.
The local processor includes a microprocessor 12 such as in the Intel 80386, a cache controller 13 such as an Intel 82385, and a high speed cache 14 implemented using storage elements such as static RAM.
A portion of the storage area in the cache controller 13 stores a cache tag which stores validity codes for corresponding data locations in the cache 14.
The local processor 11 includes a local processor port 15 to which the microprocessor 12 and cache controller 13 are connected.
The local processor port 15 is coupled through local buffer 16 to a local bus 17.
Local bus 17 is connected to system buffer 18 which provides for communication between the system bus 10 and the local bus 17 The local buffer 16 and system buffer 18 may be implemented using 74646 buffers as known in the art.
These buffers are characterized by a tristate input 19 which tristates the output of the local port outgoing buffer 20.
Further, the outgoing buffer 20 includes a pipeline register 21 and the outgoing buffer 21 on the system buffer 18 likewise includes a pipeline register 22 forming an outgoing pipeline for external write accesses.
The incoming buffer 23 on system buffer 18 includes a pipeline register 24 forming an incoming pipeline for local store write access signals coming from the system bus.
A pipeline controller 40 is coupled to the buffer 18 for controlling the inbound and outbound pipelines.
The tristate buffers have post-write pipeline registers in a conventional post-write pipeline configuration.
Thus, any write can be stored in a pipeline register to be finished later while a current bus cycle is finished.
For the system buffers 18, two way pipelining is used.
Because a single incoming write can be held in a pipeline register, a single write will not cause a deadlock