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Decoupled DMA transfer list storage technique for a peripheral resource controller
| Details |
Inventors: Jones, Craig S.; Lory, Jay; Pecone, Victor K.;
Assignee: Dell USA, L.P. (Round Rock, TX)
Primary Examiner: Harvey; Jack B.
Assistant Examiner: Phan; Raymond N.
Attorney, Agent or Firm:
A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by a decoupled DMA transfer list storage technique for a peripheral resource controller in accordance with the present invention.
In one embodiment, a peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives.
The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller.
The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer.
A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information.
The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations.
In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus.
A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface.
The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.
Since the DMA controller does not have to arbitrate for the local bus to access the DMA transfer list information, improved DMA performance may be advantageously attained, and improved local processor performance may also be attained.
In addition, since the DMA transfer list memory is not incorporated within the bus interface controller, costs may be reduced for FPGA and gate array implementations
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