Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home I/O Systems Delay-circuit-with-phase-locked-loop-control

 Renaming of virtual communication port for IR devices
FIG. 1 shows a computer system 20 having a host computer 22 connected to communicate with an ...


 Frame-to-frame compression of vector quantized signals and other post-processing
The present inventional comprises a technique for post-quantization processing. A quantizer is ...


 Vector quantization method employing mirrored input vectors to search codebook
Briefly stated, the present invention is directed to a vector quantization method that employs ...


 Image compression method and apparatus employing distortion adaptive tree search vector quantization with avoidance of transmission of redundant image data
OF THE DRAWINGS Before proceeding to the description of the drawings, it should be understood that,...


 Method and apparatus for coding image information, and method of creating code books
Accordingly, an object of the present invention is to provide an image information coding apparatus ...


 Method and apparatus for video data compression using temporally adaptive motion interpolation
One object of the invention is to provide an improved method and apparatus for video compression. A...


 Thermosetting resin composition
We claim: 1. A thermosetting resin composition comprising: (a) a film-forming polyol resin having a ...


 Missile fire-control system and method
A successful defense of a country depends preponderantly upon an efficient defense against enemy ...


 Eye contact video telephony
One embodiment of the invention comprises means for projecting onto a flat display screen images ...


 Moving vector extractor
A disadvantage to the above method is that the extraction of a moving vector is greatly influenced ...


 Delay circuit with phase locked loop control

Details
Inventors: Ngo, Duc;
Assignee: Zenith Electronics Corporation ()
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Tran; Toan
Attorney, Agent or Firm:

A delay circuit includes an output voltage controllable BICMOS delay element that is coupled to a phase locked loop that develops a control voltage. The control voltage is applied to the output BICMOS delay element and to another BICMOS delay element in the phase locked loop. An input voltage is applied to the phase locked loop and, along with the output of the phase locked loop, to the output BICMOS delay element.

DETAILED DESCRIPTION What is claimed is: 1.
A delay circuit comprising: first BICMOS delay means including voltage controllable time constant means; a source of input voltage coupled to said first BICMOS delay means; phase detector means, including a phase detector, a loop filter and an amplifier and level shifter, for receiving said input voltage and an output of said first BICMOS delay means and for producing a control voltage; means coupling said control voltage to said first BICMOS delay means for controlling said time constant means; and a second BICMOS delay means coupled to receive said input voltage and said control voltage.
2.
The circuit of claim 1 wherein said phase detector comprises an exclusive OR gate.
3.
A delay circuit comprising: first BICMOS delay means including first voltage controllable time constant means; a source of input voltage coupled to said BICMOS delay means; phase locked loop means for receiving said input voltage and an output of said first BICMOS delay means and for producing a control voltage, said phase locked loop means, including an exclusive OR gate phase detector, a loop filter and an amplifier and level shifter for developing said control voltage; a second BICMOS delay means including second voltage controllable time constant means coupled to receive said input voltage and said control voltage; and means coupling said control voltage to said first and to said second BICMOS delay means for controlling said first and said second voltage controllable time constant means.
4.
The circuit of claim 3 wherein said first and said second BICMOS delay means each comprises a delay element that includes a pair of BICMOS inverters and a timing capacitor.
5.
The circuit of claim 4 wherein each of said BICMOS delay means comprises a plurality of said delay elements.




Description:
CROSS REFERENCE TO COPENDING APPLICATIONS This application discloses inventions claimed in copending applications Ser.
No.
07/613175, entitled FREQUENCY MULTIPLIER CIRCUIT, Ser



Related patents
  BiCMOS bit line load for a memory with improved reliability
Accordingly, there is provided, in one form, a bit line load coupled to a differential bit line pair in a block of the memory. The bit line load comprises first, second, ...
  Semiconductor integrated circuit device
It is therefore an object of the present invention to provide a semiconductor integrated circuit device which optimizes the circuit and signal configuration of a memory ...
  Data protection system for electronic postage meters having multiple non-volatile multiple memories
It is an object of the present invention to provide a data protection system for an electronic postage meter having multiple NVMs. It is a further object of the present ...
  Read only memory and decode circuit
Accordingly, it is an object of this invention to provide an improved form of data path multiplexing and busing structure. It is a further object of the invention to ...
  Two stage run and string data compressor providing doubly compressed output
It is a principle object of the present invention to provide a high speed real time double data compression system employing novel expanded run length pre-encoding and ...
  Spatial bandwidth testing for digital data-compressed video systems
What is claimed is: 1. A method of spatial bandwidth testing for a digital data-compressed video system comprising the steps of: generating a complex test signal having ...
  Multiple input processor for cable television head end controller
It is therefore a general object of the present invention to provide a multiple input processor for a cable television network communications system. Another object of ...
  Method and apparatus for generating a video display from signals produced by borehole scanning
The instant invention comprises a method and apparatus for creating video display signals from information generated by acoustically scanning a reflecting boundary ...
  Endoscope-image processing apparatus for performing image processing of emphasis in endoscope image by pigment concentration distribution
It is an object of the invention to provide an endoscope-image processing apparatus capable of producing an endoscope image provided with characteristics suitable for ...
  Frame register switching for a video processor
OF THE PREFERRED EMBODIMENT FIG. 1 shows a block diagram of the video frame register interface 201 of the current invention and how it is connected to other circuitry ...

0.044

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved