Delay time checking arrangement

DETAILED DESCRIPTION Accordingly, it is an object of the present invention, to provide a delay time checking arrangement for checking the delay time in a signal propagated between first and second circuit blocks to be checked.
This time delay checking arrangement comprises clock generator means for generating a first clock signal and a second clock signal lagging behind the first clock signal said first and second clock signals having a cycle period equal to a predetermined maximum delay time, transfer means for propagating a test signal, supplied from the first circuit block in synchronism with the first clock signal, to the second circuit block; first memory means contained in said second circuit block to store the test signal in synchronism with the first clock signal; second memory means contained in the second circuit block to store the test signal in synchronism with the second clock signal; and detector means for continuing to produce a disparity signal as long as disparity is detected between the output signal of the first memory means and that of the second memory means beyond a time period of the second clock signal.
An excess time delay indication is also provided by generating a third clock signal, and by comparing this third clock signal with the disparity signal to produce an output excess time delay indicating signal whenever they occur simultaneously.