Detecting improper operation of a digital data processing apparatus

DETAILED DESCRIPTION I claim: 1.
A method of testing a digital memory apparatus that comprises a memory device having first through mth separately addressable memory locations each memory location storing a digital word having n binary digits, input means for writing a digital signal into the memory device, and means for reading the contents of each memory location out of the memory device, the method comprising applying a digital input signal having a succession of sequences of p digital words, where p is an even number less than m and is not an integral submultiple of m, to the input means, modifying the digital input signal by inserting a predetermined digital test word into the digital input signal in place of the qth word of each sequence, writing the modified sequences into the first through mth separately addressable memory locations sequentially and repeatedly, reading the contents of the first through mth memory locations sequentially and repeatedly, and comparing at least one predetermined digit of the qth digital word of each sequence read out of the memory device with other digits of that word and thereby determining whether the memory apparatus is operating properly.
2.
A method according to claim 1, wherein q is less than p/2 and the method comprises inserting a first predetermined digital test word into the digital input signal in place of the qth word of each sequence and inserting a second predetermined test word into the digital input signal in place of the (q+p/2)th word of each sequence, the second test word being the complement of the first test word, and the method further comprises comparing at least one digit of the qth and (q+p/2)th words of each sequence read out of the memory device with the other digits of that word.
3.
A method according to claim 2, further comprising inserting the second predetermined digital test word into the digital input signal in place of the (q+1)th word of each sequence and inserting the first predetermined digital test word into the digital input signal in place of the (q+p/2+1)th word of each sequence