Communications network and method which implement diversified routing |
| What is claimed is: 1. A method of sending information through a network having a plurality of ... |
|
Method of determining the topology of a network of objects |
| OF THE PREFERRED EMBODIMENTS The invention will be described by reference to its theory of ... |
|
Enabling target servers to control determination of full user synchronization |
| It is a general object of this invention to provide full synchronization on demand by a managed ... |
|
Instrument housing |
| FIG. 3 illustrates the components of the basic instrument housing 10 in accordance with this ... |
|
Release apparatus for computer mass storage devices |
| It is an object of the present invention to provide an apparatus for efficiently removing mass ... |
|
Cooling of electronic equipment cabinets |
| FIG. 1 illustrates an embodiment of the invention. The cabinet 10 includes a housing 11 and four ... |
|
Form factor adaptor |
| The present form factor adaptor overcomes many disadvantages of the prior form factor conversion ... |
|
Printed circuit board mounting cage |
| In carrying out principles of the present invention in accordance with a preferred embodiment ... |
|
Service integrated transmission system |
| It is therefore the object of the present invention to provide a method of operating a transmission ... |
|
Means to differentiate between commands and data on a communications link |
| It is therefore an object of this invention to differentiate between commands and data while ... |
|
|
Device and method for providing a simulation of an idle UART to prevent computer lockup
| Details |
Inventors: Antol, Shawn Richard; Hafez, Raed Mouaffac;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Ray; Gopal C.
Assistant Examiner:
Attorney, Agent or Firm: Stockley; Darleen J.
The invention prevents an operating system from freezing operation of computer peripherals such as a PCMCIA modem card constructed using an AT&T HSM PID2 Chipset when a suspend mode is activated by the computer. The invention provides a simulation (device: 100, 200; method: 300, 600, 700) of an idle Universal Asynchronous Receiver Transmitter, UART, in a computer peripheral operably coupled to the computer wherein the simulation provides a logic one in a least significant bit position for the PCMCIA data bus, thereby indicating that no data remains to be sent on the PCMCIA data bus. |
|
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT The present invention prevents an operating system such as Windows. RTM. 95 from freezing operation of a computer with an inserted PCMCIA modem card that was constructed using an AT&T HSM PID2 Chipset when a suspend, or sleep, mode is activated by the computer and the modem communication application is open. The invention provides a simulation of an idle Universal Asynchronous Receiver Transmitter, UART, in a computer peripheral operably coupled to the computer. The simulation provides a logic one in a least significant bit position for the data bus, thereby indicating that no interrupts need to be serviced or no data remains to be sent on the data bus. Hence, this operation prevents locking up by the operating system of the computer when the suspend mode is entered. In the preferred embodiment, the invention prevents locking up of the computer by the Windows. RTM. 95 operating system when a communications application such as ProComm Plus. RTM. or Quicklink. RTM. interacts with an AT&T HSM PID2 based PCMCIA modem card. Hence, this invention is vital to the use of AT&T HSM PID2 PCMCIA modem cards. FIG. 1, numeral 100, is a block diagram of a device in accordance with the present invention. When a computer enters a suspend mode, the device prevents an operating system from locking up the computer when a suspend, or sleep, mode is entered by providing a simulation of an idle Universal Asynchronous Receiver Transmitter, UART, for a computer peripheral operably coupled to the computer. The device includes an electrical path (102) of a data bus, for carrying a signal representing a least significant data bit and a resistor (104), coupled to the electrical path of the data bus and to a logic one voltage, for forcing the least significant data bit to become a logic one when all elements coupled to the data bus are in a high impedance state. The electrical path of the data bus is typically an electrically conductive trace, e. g. , a copper trace. The resistor is selected from an ohmic range of 2
|
|