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Details
Inventors: Guttag, Karl M.; Simpson, Richard D.; Gove, Robert J.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Powell; Mark R.
Assistant Examiner: Chauhan; U.
Attorney, Agent or Firm: Marshall, Jr.; Robert D., Kesterson; James C., Donaldson; Richard L.

A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs. Second memory has a second storage location storing the first portion of the second word accessible by the first inputs and the third set of bits received at the second inputs. Processing system includes a processor operating in a first mode to access a selected one of the first and second words and in a second mode to access a selected one of the first and second portions of both the first and second words.

DETAILED DESCRIPTION According to the invention, a processing system is provided operating on data words each having at least first and second portions.
The processing system includes a memory bank having first and second memories each associated with first and second address inputs.
The first memory includes a first storage location for storing the first portion of a first word and is accessible by a first set of address bits being received at the first inputs associated with the first memory and a second set of inputs address bits received at the second inputs associated with the first memory.
The first memory also includes a second storage location for storing the second portion of a second word and is accessible by the first set of bits being received at the first inputs associated with the first memory and a third set of bits being received at the second inputs associated with the first memory.
The second memory includes a first storage location for storing the second portion of the second word and is accessible by the first set of bits being received at the first inputs associated with the second memory and the second set of bits being received at the second set of inputs associated with the second memory.
The second memory also includes a second storage location for storing the first portion of the second word and is accessible by the first set of bits being received at the first inputs associated with the second memory and the third set of bits being received at the second set of inputs associated with the second memory.
The processing system includes a processor which is operable in a first mode to access a selected one of the first and second words by providing a corresponding first set of address bits to the first inputs associated with each of the first and second memories and a corresponding one of the second and third sets of bits to the second inputs associated with each of the first and second memories.
The processor is operable in a second mode to access a selected one of the first and second portions of both the first and second words by providing a corresponding first set of bits to the first inputs associated with each of the first and second memories, providing a selected one of the second and third sets of bits to the second inputs associated with the first memory and providing an other one of the second and third sets of bits to the second inputs associated with the second memory


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