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Hazard-free clocked master/slave flip-flop
The present invention provides a clocked master/slave flip-flop comprising a master portion having plural similar logic elements for receiving at least data and clock ...
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Carrier detect circuit
An object of the invention is to provide an improved carrier detect circuit of the type described in U.S. Pat. No. 3,593,151 for preventing false startups of printing ...
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Processor supervisory circuit and method having increased range of power-on reset signal stability
To address the above-discussed deficiencies of the prior art, the present invention provides a novel, low-cost, discrete-component processor supervisory circuit. More ...
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Low-noise frequency divider
It is an object of the invention to remedy these drawbacks to a great extent by proposing a frequency divider which generates a single parasitic signal having a unique ...
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DC-to-DC converter functioning in a pulse-skipping mode with low power consumption and PWM inhibit
OF THE PREFERRED EMBODIMENTS The numerous innovative teachings of the present application will be described with particular reference to the presently preferred ...
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AC input cell for data acquisition circuits
What is claimed is: 1. An AC input cell, comprising: a first node; a second node; a first line coupled between said first node and said second node, said first line ...
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Signal-processing multiprocessor system
It is an object of the present invention to provide a signal-processing system which makes it possible to comply with these different requirements of speed and ...
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Microcoded microprocessor with shared ram
The present invention is a system for utilizing a single RAM array as a control store for microcode, and as a memory for other functions such as, for example, memory ...
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Buffer memory device capable of memorizing operand and instruction data blocks at different block sizes
What is claimed is: 1. In a buffer memory device intermediate between a central processing unit and a main memory and operable to selectively memorize and read out an ...
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Data transfer control unit permitting data access to memory prior to completion of data transfer
What is claimed is: 1. A data transfer control unit comprising: (a) first address register means for registering a first final address value of a memory area of a memory ...
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