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Home I/O Systems Digital-processing-system-including-plural-memory-devices-and-data-transfer-circuitry

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Details
Inventors: Umina, Leonard J.; Anselmo, Robert A.;
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Examiner: Gossage; Glenn
Assistant Examiner:
Attorney, Agent or Firm: Maloney; Denis G., Cefalo; Albert P.

A digital processing system includes first and second processors and first and second random access memories (RAMs) respectively associated with the first and second processors. Each of the first and second RAMs includes a plurality of independent memory cells, each cell in the first RAM having associated therewith a corresponding cell in the second RAM. Input/output circuitry provides independent access by the first processor to the first RAM and by the second processor to the second RAM. Control logic is responsive to a transfer control signal to simultaneously transfer data stored in the memory cells of one of the first and second RAMs into the corresponding cells of the other of the first and second RAMs. Data may be selectively transferred such that only data stored in selected memory cells is transferred between the first and second RAMs.

DETAILED DESCRIPTION Additional advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The present invention overcomes the problems and disadvantages of the prior art by providing memory apparatus including random access memories respectively associated with different processors, the memory apparatus being responsive to a transfer control signal to cause the simultaneous transfer of data held in memory cells of one memory into corresponding memory cells in a different one of the memories.
In accordance with the principles of the present invention, there is provided digital memory storage apparatus, responsive to external input/output (I/O) signals and a transfer control signal.
The apparatus comprises a first and a second random access memory (RAM) means, each containing a plurality of independent memory cells, for retrievably storing digital data.
The first RAM means includes first I/O means for providing access to the digital data stored in the first RAM means in response to the I/O signals.
The second RAM means includes second I/O means for providing access to the digital data stored in the second RAM means in response to the I/O signals independently of the access to the digital data stored in the first RAM means by the first I/O means.
The apparatus further comprises control means, responsive to the transfer control signal, for simultaneously copying the digital data in the memory cells of one of the RAM means into corresponding ones of the memory cells of the other RAM means.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention



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