Digital switching system

DETAILED DESCRIPTION We claim: 1.
A system for exchanging messages between subscribers and an exchange wherein messages of serial trains of digital pulses are coupled from an exchange to each subscriber during a TRANSMIT half of a transmission frame and messages of serial bits of pulses from each of the subscribers are coupled to the exchange during the RECEIVE half of a transmission frame, said system comprising: (a) a message input array of addressable memory elements into which a first group of said pulses are written as M words of N bits; (b) a message output array of addressable memory elements into which the first group of pulses are transferred and stored as N words of M bits and are read out as M words of N bits for transmission to said subscribers; (c) signalling input and output arrays of addressable memory elements wherein at least one of said digital pulses is written into the signalling input array; and (d) a data processor for periodically reading the information in the signalling input array and transferring outgoing signalling information to said signalling output array for transmission to said subscribers.
2.
The system of claim 1 in which writing into and reading out of the message output array and writing into the message input array is performed in a fixed sequence while the reading out sequence of the message input array is varied in accordance with the desired interconnection of subscribers.
3.
The system of claim 2 including a source address array of addressable memory elements into which the processor, in response to the signalling pulses written into the signalling input array, writes information indicating connections to be made between subscribers, said source address array controlling the sequence in which the message information is transferred from the message input array to the message output array.
4.
The system of claim 1 wherein all subscribers transmit messages to the exchange, concurrently, in response to a signal sent from the exchange.
5.
The system of claim 4 wherein the signal comprises the first pulse from the signalling output array