 Partial scrolling video generator |
| OF SPECIFIC EMBODIMENTS The invention is described with reference to specific embodiments. Other ... |
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| Matrix display panel having alternating scan pulses generated within one frame scan period |
| It is an object of the present invention to provide a liquid crystal display panel having a high ... |
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| TDM system and method having time slot request signaling |
| Shown in FIG. 1 is an illustrative block diagram of a Time Division Multiplex (TDM) system 100 ... |
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| Vertical ramp automatic amplitude control |
| What is claimed is: 1. A method of producing a constant amplitude deflection ramp voltage over a ... |
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| Decision circuit operable at a wide range of voltages |
| What is claimed is: 1. A decision circuit, comprising: a first comparator which compares an input ... |
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| Communication path continuity verification arrangement |
| Time-slot Interchange Unit 11 Each of the line units transmits recurring frames each comprising 64 ... |
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| Switching regulator having low power mode responsive to load power consumption |
| A switching mode power converter monitors the level of power supplied to a load device. The ... |
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| Method for DRAM sensing current control |
| OF THE PREFERRED EMBODIMENTS OF THE INVENTION Turning first to FIG. 1, a portion of a prior art ... |
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| Sense amplifier power supply circuit |
| OF PREFERRED EMBODIMENT For the convenience of description, a sense amplifier power supply circuit ... |
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Dimm pair with data memory and state memory
| Details |
Inventors: Laudon, James P.; Lenoski, Daniel E.; Manton, John;
Assignee: Silicon Graphics, Inc. (Mountain View, CA)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Sterne, Kessler, Goldstein & Fox P.L.L.C.
A high memory capacity DIMM for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM is configured for use in a DIMM pair. In the DIMM pair, a first DIMM includes a first data memory having first and second memory bank portions for storing data, and a first state memory configured to store state information corresponding to data stored in a first memory bank. A second DIMM includes a second data memory having third and fourth memory bank portions for storing data, and a second state memory configured to store state information corresponding to data stored in a second memory bank. The first memory bank is formed from the first memory bank portion and the third memory bank portion. The second memory bank is formed from the second memory bank portion and the fourth memory bank portion. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Table of Contents I.
Overview II.
Architecture of the DIMM III.
Implementation of the DIMM in a DIMM Pair IV.
Details of the DIMM Interconnects V.
DIMM Chip Layout VI.
The Pad Description VII.
Timing Requirements VIII.
Waveform Diagrams XI.
Expanded State Memory X.
Conclusion I.
Overview The preferred embodiments of the invention are now described with reference to the figures.
While specific steps, configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only.
A person skilled in the relevant art will recognize that other steps, configurations and arrangements can be used without departing from the spirit and scope of the invention.
In a distributed, shared memory (DSM) multiprocessor such as that described in commonly-owned, copending U.
S.
patent application Ser.
No.
08/435,456, filed May 5, 1995, entitled "System and Method For Network Exploration and Access in a Multi-Processor Environment," main computer memory is distributed across a processor network.
Each distributed portion (node) of the main memory can be associated with one or more local processors.
In such a system, memory management becomes quite complex.
The DSM multiprocessor described in the above-identified application implements a directory-based cache coherence scheme that simplifies memory management.
The directory-based memory management system is described in the following commonly-owned, copending patent applications: U.
S.
patent application Ser.
No.
08/435,460, filed May 5, 1995, entitled "Directory-Based Coherence Protocol Allowing Efficient Dropping of Clean-Exclusive Data," U.
S.
patent application Ser.
No.
08/435,462, filed May 5, 1995, entitled "System and Method For a Multiprocessor Partitioning to Support High Availability," U.
S.
patent application Ser.
No.
08/435,464, filed May 5, 1995, entitled "Page Migration In a Non-Uniform Memory Access (NUMA) System," U.
S.
patent application Ser.
No.
08/435,459, filed May 5, 1995, entitled "System and Method For Maintaining Coherency of Virtual-to-Physical Memory Translations in a Multiprocessor Computer," and U
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I/O Systems 
