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Disk cache control unit
| Details |
Inventors: Kambayashi, Kosaku; Nakamura, Katsunori; Satoh, Takao; Asaka, Yoshihiro; Nagasawa, Teruo;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Shaw; Dale M.
Assistant Examiner: Shin; Christopher B.
Attorney, Agent or Firm: Antonnelli, Terry, Stout & Kraus
A disk cache control unit disposed between an upper-rank processor and a disk unit, comprising a cache memory for holding a copy of data stored in the disk unit, at least one first interface controller which checks, in response to an input/output command requesting data to be read from the upper-rank processor, whether or not the data requested by the command is stored in the cache memory, and requests a head positioning of the disk unit when the data is not stored in the cache memory, and a second interface controller which indicates head positioning to the disk unit in response to a head positioning request, notifies the completion of the head positioning to the first interface controller in response to a notice of the completion of the head positioning, and which reads data from the disk unit and stores the data in the cache memory when a data transfer request did not come in a specified time period set to read data from the disk unit without a rotational delay after a notice of the head positioning head been given to the first interface controller and the subsequent transfer of data from the second interface controller had been completed, and which gives a notice of storage of the data in the cache memory through memory means to the first interface controller, and in response to this storage notice, the first interface controller reads the data from the cache memory and transfers the data to the upper-rank processor. |
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DETAILED DESCRIPTION The object of the present invention is to provide a disk cache control unit which can reduce wasteful rotational delays on the disk unit side in the exchange of data between an upper-rank processor and a disk unit through the intermediary of a disk control unit.
The disk cache control unit according to the present invention comprises an upper-rank processor including a CPU, a main storage and a channel unit, a cache memory for holding a copy of data to be stored in the disk unit, at least one first interface controller and at least one second interface controller.
On receipt of an input/output command from the upper-rank processor asking for data to be read from the disk unit, the first interface controller examines the data stored in the cache memory, and if there is desired data stored therein, transfers the data to the upper-rank processor according to a subsequent input/output command controller, or if there is not the desired data stored in the cache memory, issues a head positioning command to the disk unit.
In response to this head positioning command, the second interface controller positions the head in the disk unit, and when the head positioning has been completed, issues information as to the completion of the head positioning.
If, in response to this, a data transfer request is given from the first interface controller to the second interface controller and a subsequent command is read, the second interface controller reads out data from the disk unit and stores the data in the cache memory, and sends the data to the first interface controller, which in turn transfers the data to the upper-rank processor.
If the first interface controller did not give a data transfer request to the second interface controller by the time a read operation of data from the second interface controller should have started after the completion of the head positioning, or even though a data transfer request has been given and the data transfer has been carried out once, if a subsequent input/output command is not given by the upper-rank processor within a specified time for reading data from the disk unit, the lower-rank interface controller stores a range of data that is requested by the initial input/output command in the cache memory and issues a request for transfer of the stored data
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