Disk drive controller with a posted write cache memory

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG.
1, the letter D general represents a disk array controller incorporating the present invention.
The disk array controller D has a local processor 30, preferably a V53 manufactured by NEC.
The local processor 30 has address bus UD, data bus UD and control bus UC outputs.
The data bus UD is connected to a transceiver 32 whose output is the local data bus LD.
The address bus UA is connected to the inputs of a buffer 34 whose outputs are connected to the local data bus LD.
The local processor 30 has associated with it random access memory (RAM) 36 coupled via the data bus UD and the address bus UA.
The RAM 36 is connected to the processor control bus UC to develop proper timing signals.
Similarly, read only memory (ROM) 38 is connected to the data bus UD, the processor address bus UA and the processor control bus UC.
Thus the local processor 30 has its own resident memory to control its operation and for its data storage.
A programmable array logic (PAL) device 40 is connected to the local processor control bus UC and to the processor address bus UA to develop additional control signals utilized in the disk array controller D.
The local processor address bus UA, the local data bus LD and the local processor control bus UC are also connected to a bus master integrated controller (BMIC) 42.
The BMIC 42 serves the function of interfacing the disk array controller D with a standard bus, such as the EISA or MCA bus and acting as a bus master.
In the preferred embodiment the BMIC 42 is interfaced with the EISA bus and is the 82355 provided by Intel.
Thus by this connection with the local processor address bus UA, the local data bus LD and the control bus UC the BMIC 42 can interface with the local processor 30 to allow data and control information to be passed between the host system and the local processor 30.
Additionally, the local data bus LD and local processor control bus UC are connected to a transfer controller 44.
The transfer controller 44 will be explained in more detail, but is generally a specialized, multichannel direct memory access (DMA) controller used to transfer data between the transfer buffer RAM 46 and the various other devices present in the disk array controller D