Dram core refresh with reduced spike current

DETAILED DESCRIPTION The present invention makes multibank refresh more practical by varying the current profile for the row sense and/or row precharge currents during a refresh operation, as compared to normal memory access.
Unlike normal memory accesses, data is not needed, and a fast access time is not required.
This allows the current to be spread using different circuitry for driving the current so as to lessen current spikes.
The spread current is still maintained within the timing of a normal refresh or memory access.
By refreshing multiple banks in response to a single command, the present invention provides a method for reducing the communication overhead over the interface bus to the memory devices for refresh operations.
In one embodiment, the generation of row and bank addresses during refresh is split between on-chip and external commands.
A row counter is provided on the memory chip, with the row counter being used for refresh operations, both normal and self-refresh.
Only the bank address needs to be sent over the memory bus.
Since the same row counter is used for self and normal refresh, only a burst of the banks for a particular row need to be issued to regain synchronization, since the same row counter is used in both modes.
Additionally, in the preferred embodiment, the banks occupy the least significant bits of the address, and the rows occupy the most significant bits of the address.
Such an addressing scheme allows the internal row counters to be taken advantage of, and allows a transition from self-refresh to normal refresh with only a burst of the banks.
In one embodiment, the row sense or precharge currents have their profile modified by using multiple transistors in parallel, with only one or some transistors being turned on, or some or all of the transistors being sequentially turned on, so that the full current is not applied at once in the refresh mode.
In normal mode, all the transistors can be turned on simultaneously for the fastest access.
Alternately, the control signal provided to the sense driver or precharge driver could be ramped at a lower rate, or operate at a lower voltage to limit the current spike of the transistor