Dual bus system with multiple processors having data coherency maintenance

DETAILED DESCRIPTION The present invention provides a specialized dual system bus capability by which different types of processor modules having different types of cache functions can be connected and integrated for efficient data transfer operations and computer processing.
Each one of the specialized dual system busses provides separate data lines for each of the functions of control, status, arbitration, clock signals, and address/command/data information transfer.
Multiple choice of bus pathways are provided for each module when it becomes a module requesting bus access.
Additionally multiple pathways are provided via the dual system busses for receipt of data when a module becomes a receiving module.
Additionally, there can be simultaneous operations wherein a single module can be both transmitting information on one system bus and receiving information on the other bus line, thus enhancing throughput.
A primary benefit of the dual bus system is the capability of operational activity for processors having Store-Through cache memory units and at the same time having the capability of using the same data transfer protocol for operating with processing units having Non-Store-Through (NST) cache capability.
The data transfer commands and protocol described herein enable the same bus to be used for one configuration involving Store-Through cache memory units in a processor or alternatively being available for operating with processing units having Non-Store-Through capability without any change in the bus structure or the bus protocol of the system.