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Dynamic address mapping for conflict-free vector access
| Details |
Inventors: Harper, III, David T.; Linebarger, Darel A.;
Assignee: Board of Regents, University of Texas System (Austin, TX)
Primary Examiner: Zache; Raulfe B.
Assistant Examiner:
Attorney, Agent or Firm: Arnold, White & Durkee
Conflict-free vector access of any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector. A respective storage scheme for each vector, for example, is selected to provide conflict-free access for a predetermined stride S. The respective storage scheme involves a rotation or permutation of an addressed row of corresponding memory locations in N parallel modules in main memory. The amount of rotation or permutation is a predetermined function of the predetermined stride S and the row address. The rotation is performed by modulo-N addition, or the permutation is performed by a set of exclusive-OR gates. For a system in which N is a power of 2 such that n=log.sub.2 N, the predetermined stride S is factored into an odd component and an even component that is a power of 2. The factorization is easily performed by a shift and count procedure, a shifter and counter, or a priority encoder. The amount of rotation or permutation is a predetermined function of the even component and the row address, and is preferably obtained by selecting a field of the row address in accordance with the maximum of s and n, and masking the selected field with a mask generated from the minimum of s and n. |
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DETAILED DESCRIPTION The primary object of the invention is to provide a method of conflict-free access to parallel memory modules in a vector processing system.
Another object of the invention is to provide a circuit for mapping address locations to physical memory locations in parallel memory modules for conflict-free access by a vector processor.
Conflict-free vector access for any constant stride is made by preselecting a storage scheme for each vector based on the accessing patterns to be used with that vector.
These accessing patterns are, for example, a stride of 1 and a predetermined stride S greater than 1 that selects the storage scheme for the vector.
By factoring the predetermined stride S into two components, one a power of 2 and the other relatively prime to 2, a storage scheme is synthesized which allows conflict-free access to the vector using the predetermined stride.
The factorization is easily performed by a shift and count procedure, a shifter and counter, or a priority encoder.
Each storage scheme involves a selected rotation or permutation of a row of corresponding memory locations in different parallel modules in main memory.
The amount of rotation or permutation for any given row is a predetermined function of the power of two component of the stride and is obtained by using the power of two component to select the amount of rotation or permutation from a field of the memory address.
Assuming that the number of memory modules N is a power of 2, the selection of the field takes into consideration one of two cases, which depend upon the number (s) of factors of 2 in the stride S.
In the first case, s is less than n=log.
sub.
2 N, and in the second case, s is greater or equal to n.
For the first case, the amount of rotation or permutation (w) is found in the address field a.
sub.
n:n+s-1.
In the second case, w is found in the address field a.
sub.
s:s+n-1.
Preferably the field selection is performed by the same circuit for both cases.
The preferred field selector circuit includes a cross-bar shifter controlled by the maximum of s and n, and a mask generator controlled by the minimum of s and n for generating a mask enabling respective single-bit outputs of the cross-bar shifter to obtain the amount of rotation or permutation w
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I/O Systems 
